kwbimage.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2008
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. */
  7. #ifndef _KWBIMAGE_H_
  8. #define _KWBIMAGE_H_
  9. #include <compiler.h>
  10. #include <stdint.h>
  11. #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config))
  12. #define MAX_TEMPBUF_LEN 32
  13. /* NAND ECC Mode */
  14. #define IBR_HDR_ECC_DEFAULT 0x00
  15. #define IBR_HDR_ECC_FORCED_HAMMING 0x01
  16. #define IBR_HDR_ECC_FORCED_RS 0x02
  17. #define IBR_HDR_ECC_DISABLED 0x03
  18. /* Boot Type - block ID */
  19. #define IBR_HDR_I2C_ID 0x4D
  20. #define IBR_HDR_SPI_ID 0x5A
  21. #define IBR_HDR_NAND_ID 0x8B
  22. #define IBR_HDR_SATA_ID 0x78
  23. #define IBR_HDR_PEX_ID 0x9C
  24. #define IBR_HDR_UART_ID 0x69
  25. #define IBR_DEF_ATTRIB 0x00
  26. /* Structure of the main header, version 0 (Kirkwood, Dove) */
  27. struct main_hdr_v0 {
  28. uint8_t blockid; /* 0x0 */
  29. uint8_t nandeccmode; /* 0x1 */
  30. uint16_t nandpagesize; /* 0x2-0x3 */
  31. uint32_t blocksize; /* 0x4-0x7 */
  32. uint32_t rsvd1; /* 0x8-0xB */
  33. uint32_t srcaddr; /* 0xC-0xF */
  34. uint32_t destaddr; /* 0x10-0x13 */
  35. uint32_t execaddr; /* 0x14-0x17 */
  36. uint8_t satapiomode; /* 0x18 */
  37. uint8_t rsvd3; /* 0x19 */
  38. uint16_t ddrinitdelay; /* 0x1A-0x1B */
  39. uint16_t rsvd2; /* 0x1C-0x1D */
  40. uint8_t ext; /* 0x1E */
  41. uint8_t checksum; /* 0x1F */
  42. };
  43. struct ext_hdr_v0_reg {
  44. uint32_t raddr;
  45. uint32_t rdata;
  46. };
  47. #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
  48. struct ext_hdr_v0 {
  49. uint32_t offset;
  50. uint8_t reserved[0x20 - sizeof(uint32_t)];
  51. struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
  52. uint8_t reserved2[7];
  53. uint8_t checksum;
  54. };
  55. struct kwb_header {
  56. struct main_hdr_v0 kwb_hdr;
  57. struct ext_hdr_v0 kwb_exthdr;
  58. };
  59. /* Structure of the main header, version 1 (Armada 370/38x/XP) */
  60. struct main_hdr_v1 {
  61. uint8_t blockid; /* 0x0 */
  62. uint8_t flags; /* 0x1 */
  63. uint16_t reserved2; /* 0x2-0x3 */
  64. uint32_t blocksize; /* 0x4-0x7 */
  65. uint8_t version; /* 0x8 */
  66. uint8_t headersz_msb; /* 0x9 */
  67. uint16_t headersz_lsb; /* 0xA-0xB */
  68. uint32_t srcaddr; /* 0xC-0xF */
  69. uint32_t destaddr; /* 0x10-0x13 */
  70. uint32_t execaddr; /* 0x14-0x17 */
  71. uint8_t options; /* 0x18 */
  72. uint8_t nandblocksize; /* 0x19 */
  73. uint8_t nandbadblklocation; /* 0x1A */
  74. uint8_t reserved4; /* 0x1B */
  75. uint16_t reserved5; /* 0x1C-0x1D */
  76. uint8_t ext; /* 0x1E */
  77. uint8_t checksum; /* 0x1F */
  78. };
  79. /*
  80. * Main header options
  81. */
  82. #define MAIN_HDR_V1_OPT_BAUD_DEFAULT 0
  83. #define MAIN_HDR_V1_OPT_BAUD_2400 0x1
  84. #define MAIN_HDR_V1_OPT_BAUD_4800 0x2
  85. #define MAIN_HDR_V1_OPT_BAUD_9600 0x3
  86. #define MAIN_HDR_V1_OPT_BAUD_19200 0x4
  87. #define MAIN_HDR_V1_OPT_BAUD_38400 0x5
  88. #define MAIN_HDR_V1_OPT_BAUD_57600 0x6
  89. #define MAIN_HDR_V1_OPT_BAUD_115200 0x7
  90. /*
  91. * Header for the optional headers, version 1 (Armada 370, Armada XP)
  92. */
  93. struct opt_hdr_v1 {
  94. uint8_t headertype;
  95. uint8_t headersz_msb;
  96. uint16_t headersz_lsb;
  97. char data[0];
  98. };
  99. /*
  100. * Public Key data in DER format
  101. */
  102. struct pubkey_der_v1 {
  103. uint8_t key[524];
  104. };
  105. /*
  106. * Signature (RSA 2048)
  107. */
  108. struct sig_v1 {
  109. uint8_t sig[256];
  110. };
  111. /*
  112. * Structure of secure header (Armada 38x)
  113. */
  114. struct secure_hdr_v1 {
  115. uint8_t headertype; /* 0x0 */
  116. uint8_t headersz_msb; /* 0x1 */
  117. uint16_t headersz_lsb; /* 0x2 - 0x3 */
  118. uint32_t reserved1; /* 0x4 - 0x7 */
  119. struct pubkey_der_v1 kak; /* 0x8 - 0x213 */
  120. uint8_t jtag_delay; /* 0x214 */
  121. uint8_t reserved2; /* 0x215 */
  122. uint16_t reserved3; /* 0x216 - 0x217 */
  123. uint32_t boxid; /* 0x218 - 0x21B */
  124. uint32_t flashid; /* 0x21C - 0x21F */
  125. struct sig_v1 hdrsig; /* 0x220 - 0x31F */
  126. struct sig_v1 imgsig; /* 0x320 - 0x41F */
  127. struct pubkey_der_v1 csk[16]; /* 0x420 - 0x24DF */
  128. struct sig_v1 csksig; /* 0x24E0 - 0x25DF */
  129. uint8_t next; /* 0x25E0 */
  130. uint8_t reserved4; /* 0x25E1 */
  131. uint16_t reserved5; /* 0x25E2 - 0x25E3 */
  132. };
  133. /*
  134. * Various values for the opt_hdr_v1->headertype field, describing the
  135. * different types of optional headers. The "secure" header contains
  136. * informations related to secure boot (encryption keys, etc.). The
  137. * "binary" header contains ARM binary code to be executed prior to
  138. * executing the main payload (usually the bootloader). This is
  139. * typically used to execute DDR3 training code. The "register" header
  140. * allows to describe a set of (address, value) tuples that are
  141. * generally used to configure the DRAM controller.
  142. */
  143. #define OPT_HDR_V1_SECURE_TYPE 0x1
  144. #define OPT_HDR_V1_BINARY_TYPE 0x2
  145. #define OPT_HDR_V1_REGISTER_TYPE 0x3
  146. #define KWBHEADER_V1_SIZE(hdr) \
  147. (((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
  148. enum kwbimage_cmd {
  149. CMD_INVALID,
  150. CMD_BOOT_FROM,
  151. CMD_NAND_ECC_MODE,
  152. CMD_NAND_PAGE_SIZE,
  153. CMD_SATA_PIO_MODE,
  154. CMD_DDR_INIT_DELAY,
  155. CMD_DATA
  156. };
  157. enum kwbimage_cmd_types {
  158. CFG_INVALID = -1,
  159. CFG_COMMAND,
  160. CFG_DATA0,
  161. CFG_DATA1
  162. };
  163. /*
  164. * functions
  165. */
  166. void init_kwb_image_type (void);
  167. /*
  168. * Byte 8 of the image header contains the version number. In the v0
  169. * header, byte 8 was reserved, and always set to 0. In the v1 header,
  170. * byte 8 has been changed to a proper field, set to 1.
  171. */
  172. static inline unsigned int image_version(void *header)
  173. {
  174. unsigned char *ptr = header;
  175. return ptr[8];
  176. }
  177. #endif /* _KWBIMAGE_H_ */