regmap.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <mapmem.h>
  9. #include <regmap.h>
  10. #include <syscon.h>
  11. #include <rand.h>
  12. #include <asm/test.h>
  13. #include <dm/test.h>
  14. #include <dm/devres.h>
  15. #include <linux/err.h>
  16. #include <test/test.h>
  17. #include <test/ut.h>
  18. /* Base test of register maps */
  19. static int dm_test_regmap_base(struct unit_test_state *uts)
  20. {
  21. struct udevice *dev;
  22. struct regmap *map;
  23. ofnode node;
  24. int i;
  25. ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
  26. map = syscon_get_regmap(dev);
  27. ut_assertok_ptr(map);
  28. ut_asserteq(1, map->range_count);
  29. ut_asserteq(0x10, map->ranges[0].start);
  30. ut_asserteq(16, map->ranges[0].size);
  31. ut_asserteq(0x10, map_to_sysmem(regmap_get_range(map, 0)));
  32. ut_assertok(uclass_get_device(UCLASS_SYSCON, 1, &dev));
  33. map = syscon_get_regmap(dev);
  34. ut_assertok_ptr(map);
  35. ut_asserteq(4, map->range_count);
  36. ut_asserteq(0x20, map->ranges[0].start);
  37. for (i = 0; i < 4; i++) {
  38. const unsigned long addr = 0x20 + 8 * i;
  39. ut_asserteq(addr, map->ranges[i].start);
  40. ut_asserteq(5 + i, map->ranges[i].size);
  41. ut_asserteq(addr, map_to_sysmem(regmap_get_range(map, i)));
  42. }
  43. /* Check that we can't pretend a different device is a syscon */
  44. ut_assertok(uclass_get_device(UCLASS_I2C, 0, &dev));
  45. map = syscon_get_regmap(dev);
  46. ut_asserteq_ptr(ERR_PTR(-ENOEXEC), map);
  47. /* A different device can be a syscon by using Linux-compat API */
  48. node = ofnode_path("/syscon@2");
  49. ut_assert(ofnode_valid(node));
  50. map = syscon_node_to_regmap(node);
  51. ut_assertok_ptr(map);
  52. ut_asserteq(4, map->range_count);
  53. ut_asserteq(0x40, map->ranges[0].start);
  54. for (i = 0; i < 4; i++) {
  55. const unsigned long addr = 0x40 + 8 * i;
  56. ut_asserteq(addr, map->ranges[i].start);
  57. ut_asserteq(5 + i, map->ranges[i].size);
  58. ut_asserteq(addr, map_to_sysmem(regmap_get_range(map, i)));
  59. }
  60. return 0;
  61. }
  62. DM_TEST(dm_test_regmap_base, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  63. /* Test we can access a regmap through syscon */
  64. static int dm_test_regmap_syscon(struct unit_test_state *uts)
  65. {
  66. struct regmap *map;
  67. map = syscon_get_regmap_by_driver_data(SYSCON0);
  68. ut_assertok_ptr(map);
  69. ut_asserteq(1, map->range_count);
  70. map = syscon_get_regmap_by_driver_data(SYSCON1);
  71. ut_assertok_ptr(map);
  72. ut_asserteq(4, map->range_count);
  73. map = syscon_get_regmap_by_driver_data(SYSCON_COUNT);
  74. ut_asserteq_ptr(ERR_PTR(-ENODEV), map);
  75. ut_asserteq(0x10, map_to_sysmem(syscon_get_first_range(SYSCON0)));
  76. ut_asserteq(0x20, map_to_sysmem(syscon_get_first_range(SYSCON1)));
  77. ut_asserteq_ptr(ERR_PTR(-ENODEV),
  78. syscon_get_first_range(SYSCON_COUNT));
  79. return 0;
  80. }
  81. DM_TEST(dm_test_regmap_syscon, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  82. /* Read/Write/Modify test */
  83. static int dm_test_regmap_rw(struct unit_test_state *uts)
  84. {
  85. struct udevice *dev;
  86. struct regmap *map;
  87. uint reg;
  88. sandbox_set_enable_memio(true);
  89. ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
  90. map = syscon_get_regmap(dev);
  91. ut_assertok_ptr(map);
  92. ut_assertok(regmap_write(map, 0, 0xcacafafa));
  93. ut_assertok(regmap_write(map, 5, 0x55aa2211));
  94. ut_assertok(regmap_read(map, 0, &reg));
  95. ut_asserteq(0xcacafafa, reg);
  96. ut_assertok(regmap_read(map, 5, &reg));
  97. ut_asserteq(0x55aa2211, reg);
  98. ut_assertok(regmap_read(map, 0, &reg));
  99. ut_asserteq(0xcacafafa, reg);
  100. ut_assertok(regmap_update_bits(map, 0, 0xff00ff00, 0x55aa2211));
  101. ut_assertok(regmap_read(map, 0, &reg));
  102. ut_asserteq(0x55ca22fa, reg);
  103. ut_assertok(regmap_update_bits(map, 5, 0x00ff00ff, 0xcacafada));
  104. ut_assertok(regmap_read(map, 5, &reg));
  105. ut_asserteq(0x55ca22da, reg);
  106. return 0;
  107. }
  108. DM_TEST(dm_test_regmap_rw, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  109. /* Get/Set test */
  110. static int dm_test_regmap_getset(struct unit_test_state *uts)
  111. {
  112. struct udevice *dev;
  113. struct regmap *map;
  114. uint reg;
  115. struct layout {
  116. u32 val0;
  117. u32 val1;
  118. u32 val2;
  119. u32 val3;
  120. };
  121. sandbox_set_enable_memio(true);
  122. ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
  123. map = syscon_get_regmap(dev);
  124. ut_assertok_ptr(map);
  125. regmap_set(map, struct layout, val0, 0xcacafafa);
  126. regmap_set(map, struct layout, val3, 0x55aa2211);
  127. ut_assertok(regmap_get(map, struct layout, val0, &reg));
  128. ut_asserteq(0xcacafafa, reg);
  129. ut_assertok(regmap_get(map, struct layout, val3, &reg));
  130. ut_asserteq(0x55aa2211, reg);
  131. return 0;
  132. }
  133. DM_TEST(dm_test_regmap_getset, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  134. /* Read polling test */
  135. static int dm_test_regmap_poll(struct unit_test_state *uts)
  136. {
  137. struct udevice *dev;
  138. struct regmap *map;
  139. uint reg;
  140. unsigned long start;
  141. ut_assertok(uclass_get_device(UCLASS_SYSCON, 0, &dev));
  142. map = syscon_get_regmap(dev);
  143. ut_assertok_ptr(map);
  144. start = get_timer(0);
  145. ut_assertok(regmap_write(map, 0, 0x0));
  146. ut_asserteq(-ETIMEDOUT,
  147. regmap_read_poll_timeout_test(map, 0, reg,
  148. (reg == 0xcacafafa),
  149. 1, 5 * CONFIG_SYS_HZ,
  150. 5 * CONFIG_SYS_HZ));
  151. ut_assert(get_timer(start) > (5 * CONFIG_SYS_HZ));
  152. return 0;
  153. }
  154. DM_TEST(dm_test_regmap_poll, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  155. struct regmaptest_priv {
  156. struct regmap *cfg_regmap; /* For testing regmap_config options. */
  157. struct regmap *fld_regmap; /* For testing regmap fields. */
  158. struct regmap_field **fields;
  159. };
  160. static const struct reg_field field_cfgs[] = {
  161. {
  162. .reg = 0,
  163. .lsb = 0,
  164. .msb = 6,
  165. },
  166. {
  167. .reg = 2,
  168. .lsb = 4,
  169. .msb = 12,
  170. },
  171. {
  172. .reg = 2,
  173. .lsb = 12,
  174. .msb = 15,
  175. }
  176. };
  177. #define REGMAP_TEST_BUF_START 0
  178. #define REGMAP_TEST_BUF_SZ 5
  179. static int remaptest_probe(struct udevice *dev)
  180. {
  181. struct regmaptest_priv *priv = dev_get_priv(dev);
  182. struct regmap *regmap;
  183. struct regmap_field *field;
  184. struct regmap_config cfg;
  185. int i;
  186. static const int n = ARRAY_SIZE(field_cfgs);
  187. /*
  188. * To exercise all the regmap config options, create a regmap that
  189. * points to a custom memory area instead of the one defined in device
  190. * tree. Use 2-byte elements. To allow directly indexing into the
  191. * elements, use an offset shift of 1. So, accessing offset 1 gets the
  192. * element at index 1 at memory location 2.
  193. *
  194. * REGMAP_TEST_BUF_SZ is the number of elements, so we need to multiply
  195. * it by 2 because r_size expects number of bytes.
  196. */
  197. cfg.reg_offset_shift = 1;
  198. cfg.r_start = REGMAP_TEST_BUF_START;
  199. cfg.r_size = REGMAP_TEST_BUF_SZ * 2;
  200. cfg.width = REGMAP_SIZE_16;
  201. regmap = devm_regmap_init(dev, NULL, NULL, &cfg);
  202. if (IS_ERR(regmap))
  203. return PTR_ERR(regmap);
  204. priv->cfg_regmap = regmap;
  205. memset(&cfg, 0, sizeof(struct regmap_config));
  206. cfg.width = REGMAP_SIZE_16;
  207. regmap = devm_regmap_init(dev, NULL, NULL, &cfg);
  208. if (IS_ERR(regmap))
  209. return PTR_ERR(regmap);
  210. priv->fld_regmap = regmap;
  211. priv->fields = devm_kzalloc(dev, sizeof(struct regmap_field *) * n,
  212. GFP_KERNEL);
  213. if (!priv->fields)
  214. return -ENOMEM;
  215. for (i = 0 ; i < n; i++) {
  216. field = devm_regmap_field_alloc(dev, priv->fld_regmap,
  217. field_cfgs[i]);
  218. if (IS_ERR(field))
  219. return PTR_ERR(field);
  220. priv->fields[i] = field;
  221. }
  222. return 0;
  223. }
  224. static const struct udevice_id regmaptest_ids[] = {
  225. { .compatible = "sandbox,regmap_test" },
  226. { }
  227. };
  228. U_BOOT_DRIVER(regmap_test) = {
  229. .name = "regmaptest_drv",
  230. .of_match = regmaptest_ids,
  231. .id = UCLASS_NOP,
  232. .probe = remaptest_probe,
  233. .priv_auto_alloc_size = sizeof(struct regmaptest_priv),
  234. };
  235. static int dm_test_devm_regmap(struct unit_test_state *uts)
  236. {
  237. int i = 0;
  238. u32 val;
  239. u16 pattern[REGMAP_TEST_BUF_SZ];
  240. u16 *buffer;
  241. struct udevice *dev;
  242. struct regmaptest_priv *priv;
  243. sandbox_set_enable_memio(true);
  244. /*
  245. * Map the memory area the regmap should point to so we can make sure
  246. * the writes actually go to that location.
  247. */
  248. buffer = map_physmem(REGMAP_TEST_BUF_START,
  249. REGMAP_TEST_BUF_SZ * 2, MAP_NOCACHE);
  250. ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "regmap-test_0",
  251. &dev));
  252. priv = dev_get_priv(dev);
  253. srand(get_ticks() + rand());
  254. for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
  255. pattern[i] = rand();
  256. ut_assertok(regmap_write(priv->cfg_regmap, i, pattern[i]));
  257. }
  258. for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
  259. ut_assertok(regmap_read(priv->cfg_regmap, i, &val));
  260. ut_asserteq(val, buffer[i]);
  261. ut_asserteq(val, pattern[i]);
  262. }
  263. ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
  264. val));
  265. ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
  266. &val));
  267. ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, -1, val));
  268. ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, -1, &val));
  269. return 0;
  270. }
  271. DM_TEST(dm_test_devm_regmap, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
  272. static int test_one_field(struct unit_test_state *uts,
  273. struct regmap *regmap,
  274. struct regmap_field *field,
  275. struct reg_field field_cfg)
  276. {
  277. int j;
  278. unsigned int val;
  279. int mask = (1 << (field_cfg.msb - field_cfg.lsb + 1)) - 1;
  280. int shift = field_cfg.lsb;
  281. ut_assertok(regmap_write(regmap, field_cfg.reg, 0));
  282. ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
  283. ut_asserteq(0, val);
  284. for (j = 0; j <= mask; j++) {
  285. ut_assertok(regmap_field_write(field, j));
  286. ut_assertok(regmap_field_read(field, &val));
  287. ut_asserteq(j, val);
  288. ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
  289. ut_asserteq(j << shift, val);
  290. }
  291. ut_assertok(regmap_field_write(field, mask + 1));
  292. ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
  293. ut_asserteq(0, val);
  294. ut_assertok(regmap_field_write(field, 0xFFFF));
  295. ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
  296. ut_asserteq(mask << shift, val);
  297. ut_assertok(regmap_write(regmap, field_cfg.reg, 0xFFFF));
  298. ut_assertok(regmap_field_write(field, 0));
  299. ut_assertok(regmap_read(regmap, field_cfg.reg, &val));
  300. ut_asserteq(0xFFFF & ~(mask << shift), val);
  301. return 0;
  302. }
  303. static int dm_test_devm_regmap_field(struct unit_test_state *uts)
  304. {
  305. int i, rc;
  306. struct udevice *dev;
  307. struct regmaptest_priv *priv;
  308. ut_assertok(uclass_get_device_by_name(UCLASS_NOP, "regmap-test_0",
  309. &dev));
  310. priv = dev_get_priv(dev);
  311. sandbox_set_enable_memio(true);
  312. for (i = 0 ; i < ARRAY_SIZE(field_cfgs); i++) {
  313. rc = test_one_field(uts, priv->fld_regmap, priv->fields[i],
  314. field_cfgs[i]);
  315. if (rc)
  316. break;
  317. }
  318. return 0;
  319. }
  320. DM_TEST(dm_test_devm_regmap_field, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);