pmic.c 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Tests for the driver model pmic API
  4. *
  5. * Copyright (c) 2015 Samsung Electronics
  6. * Przemyslaw Marczak <p.marczak@samsung.com>
  7. */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <dm.h>
  11. #include <fdtdec.h>
  12. #include <fsl_pmic.h>
  13. #include <malloc.h>
  14. #include <dm/device-internal.h>
  15. #include <dm/root.h>
  16. #include <dm/test.h>
  17. #include <dm/uclass-internal.h>
  18. #include <dm/util.h>
  19. #include <power/pmic.h>
  20. #include <power/sandbox_pmic.h>
  21. #include <test/test.h>
  22. #include <test/ut.h>
  23. /* Test PMIC get method */
  24. static inline int power_pmic_get(struct unit_test_state *uts, char *name)
  25. {
  26. struct udevice *dev;
  27. ut_assertok(pmic_get(name, &dev));
  28. ut_assertnonnull(dev);
  29. /* Check PMIC's name */
  30. ut_asserteq_str(name, dev->name);
  31. return 0;
  32. }
  33. /* Test PMIC get method */
  34. static int dm_test_power_pmic_get(struct unit_test_state *uts)
  35. {
  36. power_pmic_get(uts, "sandbox_pmic");
  37. return 0;
  38. }
  39. DM_TEST(dm_test_power_pmic_get, UT_TESTF_SCAN_FDT);
  40. /* PMIC get method - MC34708 - for 3 bytes transmission */
  41. static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
  42. {
  43. power_pmic_get(uts, "pmic@41");
  44. return 0;
  45. }
  46. DM_TEST(dm_test_power_pmic_mc34708_get, UT_TESTF_SCAN_FDT);
  47. /* Test PMIC I/O */
  48. static int dm_test_power_pmic_io(struct unit_test_state *uts)
  49. {
  50. const char *name = "sandbox_pmic";
  51. uint8_t out_buffer, in_buffer;
  52. struct udevice *dev;
  53. int reg_count, i;
  54. ut_assertok(pmic_get(name, &dev));
  55. reg_count = pmic_reg_count(dev);
  56. ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
  57. /*
  58. * Test PMIC I/O - write and read a loop counter.
  59. * usually we can't write to all PMIC's registers in the real hardware,
  60. * but we can to the sandbox pmic.
  61. */
  62. for (i = 0; i < reg_count; i++) {
  63. out_buffer = i;
  64. ut_assertok(pmic_write(dev, i, &out_buffer, 1));
  65. ut_assertok(pmic_read(dev, i, &in_buffer, 1));
  66. ut_asserteq(out_buffer, in_buffer);
  67. }
  68. return 0;
  69. }
  70. DM_TEST(dm_test_power_pmic_io, UT_TESTF_SCAN_FDT);
  71. #define MC34708_PMIC_REG_COUNT 64
  72. #define MC34708_PMIC_TEST_VAL 0x125534
  73. static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
  74. {
  75. struct udevice *dev;
  76. int reg_count;
  77. ut_assertok(pmic_get("pmic@41", &dev));
  78. /* Check number of PMIC registers */
  79. reg_count = pmic_reg_count(dev);
  80. ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
  81. return 0;
  82. }
  83. DM_TEST(dm_test_power_pmic_mc34708_regs_check, UT_TESTF_SCAN_FDT);
  84. static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
  85. {
  86. struct udevice *dev;
  87. int val;
  88. ut_assertok(pmic_get("pmic@41", &dev));
  89. /* Check if single 3 byte read is successful */
  90. val = pmic_reg_read(dev, REG_POWER_CTL2);
  91. ut_asserteq(val, 0x422100);
  92. /* Check if RW works */
  93. val = 0;
  94. ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
  95. ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
  96. val = pmic_reg_read(dev, REG_RTC_TIME);
  97. ut_asserteq(val, MC34708_PMIC_TEST_VAL);
  98. pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
  99. val = pmic_reg_read(dev, REG_POWER_CTL2);
  100. ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
  101. return 0;
  102. }
  103. DM_TEST(dm_test_power_pmic_mc34708_rw_val, UT_TESTF_SCAN_FDT);