ecc.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Eastman Kodak Company, <www.kodak.com>
  5. * Michael Zaidman, <michael.zaidman@kodak.com>
  6. *
  7. * The code is based on the cpu/mpc83xx/ecc.c written by
  8. * Dave Liu <daveliu@freescale.com>
  9. */
  10. #include <common.h>
  11. #include <cpu_func.h>
  12. #include <irq_func.h>
  13. #include <log.h>
  14. #include <mpc83xx.h>
  15. #include <watchdog.h>
  16. #include <asm/io.h>
  17. #include <post.h>
  18. #if CONFIG_POST & CONFIG_SYS_POST_ECC
  19. /*
  20. * We use the RAW I/O accessors where possible in order to
  21. * achieve performance goal, since the test's execution time
  22. * affects the board start up time.
  23. */
  24. static inline void ecc_clear(ddr83xx_t *ddr)
  25. {
  26. /* Clear capture registers */
  27. __raw_writel(0, &ddr->capture_address);
  28. __raw_writel(0, &ddr->capture_data_hi);
  29. __raw_writel(0, &ddr->capture_data_lo);
  30. __raw_writel(0, &ddr->capture_ecc);
  31. __raw_writel(0, &ddr->capture_attributes);
  32. /* Clear SBEC and set SBET to 1 */
  33. out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);
  34. /* Clear Error Detect register */
  35. out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\
  36. ECC_ERROR_DETECT_MBE |\
  37. ECC_ERROR_DETECT_SBE |\
  38. ECC_ERROR_DETECT_MSE);
  39. isync();
  40. }
  41. int ecc_post_test(int flags)
  42. {
  43. int ret = 0;
  44. int int_state;
  45. int errbit;
  46. u32 pattern[2], writeback[2], retval[2];
  47. ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr;
  48. volatile u64 *addr = (u64 *)CONFIG_SYS_POST_ECC_START_ADDR;
  49. /* The pattern is written into memory to generate error */
  50. pattern[0] = 0xfedcba98UL;
  51. pattern[1] = 0x76543210UL;
  52. /* After injecting error, re-initialize the memory with the value */
  53. writeback[0] = ~pattern[0];
  54. writeback[1] = ~pattern[1];
  55. /* Check if ECC is enabled */
  56. if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) {
  57. debug("DDR's ECC is not enabled, skipping the ECC POST.\n");
  58. return 0;
  59. }
  60. int_state = disable_interrupts();
  61. icache_enable();
  62. #ifdef CONFIG_DDR_32BIT
  63. /* It seems like no one really uses the CONFIG_DDR_32BIT mode */
  64. #error "Add ECC POST support for CONFIG_DDR_32BIT here!"
  65. #else
  66. for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
  67. addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
  68. WATCHDOG_RESET();
  69. ecc_clear(ddr);
  70. /* Enable error injection */
  71. setbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
  72. sync();
  73. isync();
  74. /* Set bit to be injected */
  75. if (errbit < 32) {
  76. __raw_writel(1 << errbit, &ddr->data_err_inject_lo);
  77. __raw_writel(0, &ddr->data_err_inject_hi);
  78. } else {
  79. __raw_writel(0, &ddr->data_err_inject_lo);
  80. __raw_writel(1<<(errbit-32), &ddr->data_err_inject_hi);
  81. }
  82. sync();
  83. isync();
  84. /* Write memory location injecting SBE */
  85. ppcDWstore((u32*)addr, pattern);
  86. sync();
  87. /* Disable error injection */
  88. clrbits_be32(&ddr->ecc_err_inject, ECC_ERR_INJECT_EIEN);
  89. sync();
  90. isync();
  91. /* Data read should generate SBE */
  92. ppcDWload((u32*)addr, retval);
  93. sync();
  94. if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) ||
  95. (__raw_readl(&ddr->data_err_inject_hi) !=
  96. (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) ||
  97. (__raw_readl(&ddr->data_err_inject_lo) !=
  98. (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) {
  99. post_log("ECC failed to detect SBE error at %08x, "
  100. "SBE injection mask %08x-%08x, wrote "
  101. "%08x-%08x, read %08x-%08x\n", addr,
  102. ddr->data_err_inject_hi,
  103. ddr->data_err_inject_lo,
  104. pattern[0], pattern[1],
  105. retval[0], retval[1]);
  106. printf("ERR_DETECT Reg: %08x\n", ddr->err_detect);
  107. printf("ECC CAPTURE_DATA Reg: %08x-%08x\n",
  108. ddr->capture_data_hi, ddr->capture_data_lo);
  109. ret = 1;
  110. break;
  111. }
  112. /* Re-initialize the ECC memory */
  113. ppcDWstore((u32*)addr, writeback);
  114. sync();
  115. isync();
  116. errbit %= 63;
  117. }
  118. #endif /* !CONFIG_DDR_32BIT */
  119. ecc_clear(ddr);
  120. icache_disable();
  121. if (int_state)
  122. enable_interrupts();
  123. return ret;
  124. }
  125. #endif