zynqmp_firmware.h 2.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Xilinx Zynq MPSoC Firmware driver
  4. *
  5. * Copyright (C) 2018-2019 Xilinx, Inc.
  6. */
  7. #ifndef _ZYNQMP_FIRMWARE_H_
  8. #define _ZYNQMP_FIRMWARE_H_
  9. enum pm_api_id {
  10. PM_GET_API_VERSION = 1,
  11. PM_SET_CONFIGURATION,
  12. PM_GET_NODE_STATUS,
  13. PM_GET_OPERATING_CHARACTERISTIC,
  14. PM_REGISTER_NOTIFIER,
  15. PM_REQUEST_SUSPEND,
  16. PM_SELF_SUSPEND,
  17. PM_FORCE_POWERDOWN,
  18. PM_ABORT_SUSPEND,
  19. PM_REQUEST_WAKEUP,
  20. PM_SET_WAKEUP_SOURCE,
  21. PM_SYSTEM_SHUTDOWN,
  22. PM_REQUEST_NODE,
  23. PM_RELEASE_NODE,
  24. PM_SET_REQUIREMENT,
  25. PM_SET_MAX_LATENCY,
  26. PM_RESET_ASSERT,
  27. PM_RESET_GET_STATUS,
  28. PM_MMIO_WRITE,
  29. PM_MMIO_READ,
  30. PM_PM_INIT_FINALIZE,
  31. PM_FPGA_LOAD,
  32. PM_FPGA_GET_STATUS,
  33. PM_GET_CHIPID,
  34. PM_SECURE_SHA = 26,
  35. PM_SECURE_RSA,
  36. PM_PINCTRL_REQUEST,
  37. PM_PINCTRL_RELEASE,
  38. PM_PINCTRL_GET_FUNCTION,
  39. PM_PINCTRL_SET_FUNCTION,
  40. PM_PINCTRL_CONFIG_PARAM_GET,
  41. PM_PINCTRL_CONFIG_PARAM_SET,
  42. PM_IOCTL,
  43. PM_QUERY_DATA,
  44. PM_CLOCK_ENABLE,
  45. PM_CLOCK_DISABLE,
  46. PM_CLOCK_GETSTATE,
  47. PM_CLOCK_SETDIVIDER,
  48. PM_CLOCK_GETDIVIDER,
  49. PM_CLOCK_SETRATE,
  50. PM_CLOCK_GETRATE,
  51. PM_CLOCK_SETPARENT,
  52. PM_CLOCK_GETPARENT,
  53. PM_SECURE_IMAGE,
  54. PM_FPGA_READ = 46,
  55. PM_SECURE_AES,
  56. PM_CLOCK_PLL_GETPARAM = 49,
  57. PM_REGISTER_ACCESS = 52,
  58. PM_EFUSE_ACCESS,
  59. PM_FEATURE_CHECK = 63,
  60. PM_API_MAX,
  61. };
  62. enum pm_query_id {
  63. PM_QID_INVALID = 0,
  64. PM_QID_CLOCK_GET_NAME = 1,
  65. PM_QID_CLOCK_GET_TOPOLOGY = 2,
  66. PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
  67. PM_QID_CLOCK_GET_PARENTS = 4,
  68. PM_QID_CLOCK_GET_ATTRIBUTES = 5,
  69. PM_QID_PINCTRL_GET_NUM_PINS = 6,
  70. PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
  71. PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
  72. PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
  73. PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
  74. PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
  75. PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
  76. PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
  77. };
  78. #define PM_SIP_SVC 0xc2000000
  79. #define ZYNQMP_PM_VERSION_MAJOR 1
  80. #define ZYNQMP_PM_VERSION_MINOR 0
  81. #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
  82. #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
  83. #define ZYNQMP_PM_VERSION \
  84. ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
  85. ZYNQMP_PM_VERSION_MINOR)
  86. #define ZYNQMP_PM_VERSION_INVALID ~0
  87. #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
  88. /*
  89. * Return payload size
  90. * Not every firmware call expects the same amount of return bytes, however the
  91. * firmware driver always copies 5 bytes from RX buffer to the ret_payload
  92. * buffer. Therefore allocating with this defined value is recommended to avoid
  93. * overflows.
  94. */
  95. #define PAYLOAD_ARG_CNT 5U
  96. unsigned int zynqmp_firmware_version(void);
  97. void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
  98. int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
  99. u32 arg3, u32 *ret_payload);
  100. #endif /* _ZYNQMP_FIRMWARE_H_ */