w83c553f.h 6.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2000
  4. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  5. */
  6. /* winbond access routines and defines*/
  7. /* from the winbond data sheet -
  8. The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
  9. Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
  10. */
  11. /*ISA bridge configuration space*/
  12. #define W83C553F_VID 0x10AD
  13. #define W83C553F_DID 0x0565
  14. #define WINBOND_PCICONTR 0x40 /*pci control reg*/
  15. #define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
  16. #define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
  17. #define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
  18. #define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
  19. #define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
  20. #define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
  21. #define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
  22. #define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
  23. #define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
  24. #define WINBOND_CDR 0x4c /*Clock Divisor Register*/
  25. #define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
  26. #define WINBOND_ATSCR 0x4e /*AT System Control register*/
  27. #define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
  28. #define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
  29. #define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
  30. #define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
  31. #define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
  32. #define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
  33. #define IPADCR_MBE512 0x1
  34. #define IPADCR_MBE640 0x2
  35. #define IPADCR_IPATOM4 0x10
  36. #define IPADCR_IPATOM5 0x20
  37. #define IPADCR_IPATOM6 0x40
  38. #define IPADCR_IPATOM7 0x80
  39. #define CSCR_UBIOSCSE 0x10
  40. #define CSCR_BIOSWP 0x20
  41. #define IDECSR_P0EN 0x01
  42. #define IDECSR_P0F16 0x02
  43. #define IDECSR_P1EN 0x10
  44. #define IDECSR_P1F16 0x20
  45. #define IDECSR_LEGIRQ 0x800
  46. /*
  47. * Interrupt controller
  48. */
  49. #define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20
  50. #define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21
  51. #define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21
  52. #define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21
  53. #define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21
  54. #define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20
  55. #define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20
  56. #define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0
  57. #define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0
  58. #define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1
  59. #define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1
  60. #define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1
  61. #define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1
  62. #define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0
  63. #define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0
  64. #define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1
  65. #define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43
  66. /*
  67. * DMA controller
  68. */
  69. #define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */
  70. #define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */
  71. /* command/status register bit definitions */
  72. #define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
  73. #define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
  74. #define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
  75. #define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
  76. #define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
  77. #define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
  78. #define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
  79. #define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
  80. #define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
  81. #define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
  82. #define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
  83. #define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
  84. /* mode register bit definitions */
  85. #define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
  86. #define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
  87. #define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
  88. #define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
  89. #define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
  90. #define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
  91. #define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
  92. #define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
  93. #define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
  94. #define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
  95. #define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
  96. #define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
  97. #define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
  98. #define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
  99. /* request register bit definitions */
  100. #define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
  101. #define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
  102. #define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
  103. #define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
  104. #define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
  105. /* write single mask bit register bit definitions */
  106. #define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
  107. #define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
  108. #define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
  109. #define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
  110. #define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
  111. /* read/write all mask bits register bit definitions */
  112. #define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
  113. #define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
  114. #define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
  115. #define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
  116. /* typedefs */
  117. #define W83C553F_DMA1_CS 0x8
  118. #define W83C553F_DMA1_WR 0x9
  119. #define W83C553F_DMA1_WSMB 0xA
  120. #define W83C553F_DMA1_WM 0xB
  121. #define W83C553F_DMA1_CBP 0xC
  122. #define W83C553F_DMA1_MC 0xD
  123. #define W83C553F_DMA1_CM 0xE
  124. #define W83C553F_DMA1_RWAMB 0xF
  125. #define W83C553F_DMA2_CS 0x10
  126. #define W83C553F_DMA2_WR 0x12
  127. #define W83C553F_DMA2_WSMB 0x14
  128. #define W83C553F_DMA2_WM 0x16
  129. #define W83C553F_DMA2_CBP 0x18
  130. #define W83C553F_DMA2_MC 0x1A
  131. #define W83C553F_DMA2_CM 0x1C
  132. #define W83C553F_DMA2_RWAMB 0x1E
  133. void initialise_w83c553f(void);