sym53c8xx.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2001
  4. * Denis Peter, MPL AG Switzerland
  5. *
  6. * Most of these definitions are derived from
  7. * linux/drivers/scsi/sym53c8xx_defs.h
  8. */
  9. #ifndef _SYM53C8XX_DEFS_H
  10. #define _SYM53C8XX_DEFS_H
  11. #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
  12. #define SCNTL1 0x01 /* no reset */
  13. #define ISCON 0x10 /* connected to scsi */
  14. #define CRST 0x08 /* force reset */
  15. #define IARB 0x02 /* immediate arbitration */
  16. #define SCNTL2 0x02 /* no disconnect expected */
  17. #define SDU 0x80 /* cmd: disconnect will raise error */
  18. #define CHM 0x40 /* sta: chained mode */
  19. #define WSS 0x08 /* sta: wide scsi send [W]*/
  20. #define WSR 0x01 /* sta: wide scsi received [W]*/
  21. #define SCNTL3 0x03 /* cnf system clock dependent */
  22. #define EWS 0x08 /* cmd: enable wide scsi [W]*/
  23. #define ULTRA 0x80 /* cmd: ULTRA enable */
  24. /* bits 0-2, 7 rsvd for C1010 */
  25. #define SCID 0x04 /* cnf host adapter scsi address */
  26. #define RRE 0x40 /* r/w:e enable response to resel. */
  27. #define SRE 0x20 /* r/w:e enable response to select */
  28. #define SXFER 0x05 /* ### Sync speed and count */
  29. /* bits 6-7 rsvd for C1010 */
  30. #define SDID 0x06 /* ### Destination-ID */
  31. #define GPREG 0x07 /* ??? IO-Pins */
  32. #define SFBR 0x08 /* ### First byte in phase */
  33. #define SOCL 0x09
  34. #define CREQ 0x80 /* r/w: SCSI-REQ */
  35. #define CACK 0x40 /* r/w: SCSI-ACK */
  36. #define CBSY 0x20 /* r/w: SCSI-BSY */
  37. #define CSEL 0x10 /* r/w: SCSI-SEL */
  38. #define CATN 0x08 /* r/w: SCSI-ATN */
  39. #define CMSG 0x04 /* r/w: SCSI-MSG */
  40. #define CC_D 0x02 /* r/w: SCSI-C_D */
  41. #define CI_O 0x01 /* r/w: SCSI-I_O */
  42. #define SSID 0x0a
  43. #define SBCL 0x0b
  44. #define DSTAT 0x0c
  45. #define DFE 0x80 /* sta: dma fifo empty */
  46. #define MDPE 0x40 /* int: master data parity error */
  47. #define BF 0x20 /* int: script: bus fault */
  48. #define ABRT 0x10 /* int: script: command aborted */
  49. #define SSI 0x08 /* int: script: single step */
  50. #define SIR 0x04 /* int: script: interrupt instruct. */
  51. #define IID 0x01 /* int: script: illegal instruct. */
  52. #define SSTAT0 0x0d
  53. #define ILF 0x80 /* sta: data in SIDL register lsb */
  54. #define ORF 0x40 /* sta: data in SODR register lsb */
  55. #define OLF 0x20 /* sta: data in SODL register lsb */
  56. #define AIP 0x10 /* sta: arbitration in progress */
  57. #define LOA 0x08 /* sta: arbitration lost */
  58. #define WOA 0x04 /* sta: arbitration won */
  59. #define IRST 0x02 /* sta: scsi reset signal */
  60. #define SDP 0x01 /* sta: scsi parity signal */
  61. #define SSTAT1 0x0e
  62. #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
  63. #define SSTAT2 0x0f
  64. #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
  65. #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
  66. #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
  67. #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
  68. #define LDSC 0x02 /* sta: disconnect & reconnect */
  69. #define DSA 0x10 /* --> Base page */
  70. #define DSA1 0x11
  71. #define DSA2 0x12
  72. #define DSA3 0x13
  73. #define ISTAT 0x14 /* --> Main Command and status */
  74. #define CABRT 0x80 /* cmd: abort current operation */
  75. #define SRST 0x40 /* mod: reset chip */
  76. #define SIGP 0x20 /* r/w: message from host to ncr */
  77. #define SEM 0x10 /* r/w: message between host + ncr */
  78. #define CON 0x08 /* sta: connected to scsi */
  79. #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
  80. #define SIP 0x02 /* sta: scsi-interrupt */
  81. #define DIP 0x01 /* sta: host/script interrupt */
  82. #define CTEST0 0x18
  83. #define CTEST1 0x19
  84. #define CTEST2 0x1a
  85. #define CSIGP 0x40
  86. /* bits 0-2,7 rsvd for C1010 */
  87. #define CTEST3 0x1b
  88. #define FLF 0x08 /* cmd: flush dma fifo */
  89. #define CLF 0x04 /* cmd: clear dma fifo */
  90. #define FM 0x02 /* mod: fetch pin mode */
  91. #define WRIE 0x01 /* mod: write and invalidate enable */
  92. /* bits 4-7 rsvd for C1010 */
  93. #define DFIFO 0x20
  94. #define CTEST4 0x21
  95. #define BDIS 0x80 /* mod: burst disable */
  96. #define MPEE 0x08 /* mod: master parity error enable */
  97. #define CTEST5 0x22
  98. #define DFS 0x20 /* mod: dma fifo size */
  99. /* bits 0-1, 3-7 rsvd for C1010 */
  100. #define CTEST6 0x23
  101. #define DBC 0x24 /* ### Byte count and command */
  102. #define DNAD 0x28 /* ### Next command register */
  103. #define DSP 0x2c /* --> Script Pointer */
  104. #define DSPS 0x30 /* --> Script pointer save/opcode#2 */
  105. #define SCRATCHA 0x34 /* Temporary register a */
  106. #define SCRATCHA1 0x35
  107. #define SCRATCHA2 0x36
  108. #define SCRATCHA3 0x37
  109. #define DMODE 0x38
  110. #define BL_2 0x80 /* mod: burst length shift value +2 */
  111. #define BL_1 0x40 /* mod: burst length shift value +1 */
  112. #define ERL 0x08 /* mod: enable read line */
  113. #define ERMP 0x04 /* mod: enable read multiple */
  114. #define BOF 0x02 /* mod: burst op code fetch */
  115. #define MAN 0x01 /* mod: manual start */
  116. #define DIEN 0x39
  117. #define SBR 0x3a
  118. #define DCNTL 0x3b /* --> Script execution control */
  119. #define CLSE 0x80 /* mod: cache line size enable */
  120. #define PFF 0x40 /* cmd: pre-fetch flush */
  121. #define PFEN 0x20 /* mod: pre-fetch enable */
  122. #define SSM 0x10 /* mod: single step mode */
  123. #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
  124. #define STD 0x04 /* cmd: start dma mode */
  125. #define IRQD 0x02 /* mod: irq disable */
  126. #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
  127. /* bits 0-1 rsvd for C1010 */
  128. #define ADDER 0x3c
  129. #define SIEN 0x40 /* -->: interrupt enable */
  130. #define SIST 0x42 /* <--: interrupt status */
  131. #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
  132. #define STO 0x0400/* sta: timeout (select) */
  133. #define GEN 0x0200/* sta: timeout (general) */
  134. #define HTH 0x0100/* sta: timeout (handshake) */
  135. #define MA 0x80 /* sta: phase mismatch */
  136. #define CMP 0x40 /* sta: arbitration complete */
  137. #define SEL 0x20 /* sta: selected by another device */
  138. #define RSL 0x10 /* sta: reselected by another device*/
  139. #define SGE 0x08 /* sta: gross error (over/underflow)*/
  140. #define UDC 0x04 /* sta: unexpected disconnect */
  141. #define RST 0x02 /* sta: scsi bus reset detected */
  142. #define PAR 0x01 /* sta: scsi parity error */
  143. #define SLPAR 0x44
  144. #define SWIDE 0x45
  145. #define MACNTL 0x46
  146. #define GPCNTL 0x47
  147. #define STIME0 0x48 /* cmd: timeout for select&handshake*/
  148. #define STIME1 0x49 /* cmd: timeout user defined */
  149. #define RESPID 0x4a /* sta: Reselect-IDs */
  150. #define STEST0 0x4c
  151. #define STEST1 0x4d
  152. #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
  153. #define DBLEN 0x08 /* clock doubler running */
  154. #define DBLSEL 0x04 /* clock doubler selected */
  155. #define STEST2 0x4e
  156. #define ROF 0x40 /* reset scsi offset (after gross error!) */
  157. #define EXT 0x02 /* extended filtering */
  158. #define STEST3 0x4f
  159. #define TE 0x80 /* c: tolerAnt enable */
  160. #define HSC 0x20 /* c: Halt SCSI Clock */
  161. #define CSF 0x02 /* c: clear scsi fifo */
  162. #define SIDL 0x50 /* Lowlevel: latched from scsi data */
  163. #define STEST4 0x52
  164. #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
  165. #define SMODE_HVD 0x40 /* High Voltage Differential */
  166. #define SMODE_SE 0x80 /* Single Ended */
  167. #define SMODE_LVD 0xc0 /* Low Voltage Differential */
  168. #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
  169. /* bits 0-5 rsvd for C1010 */
  170. #define SODL 0x54 /* Lowlevel: data out to scsi data */
  171. #define SBDL 0x58 /* Lowlevel: data from scsi data */
  172. /*-----------------------------------------------------------
  173. **
  174. ** Utility macros for the script.
  175. **
  176. **-----------------------------------------------------------
  177. */
  178. #define REG(r) (r)
  179. /*-----------------------------------------------------------
  180. **
  181. ** SCSI phases
  182. **
  183. ** DT phases illegal for ncr driver.
  184. **
  185. **-----------------------------------------------------------
  186. */
  187. #define SCR_DATA_OUT 0x00000000
  188. #define SCR_DATA_IN 0x01000000
  189. #define SCR_COMMAND 0x02000000
  190. #define SCR_STATUS 0x03000000
  191. #define SCR_DT_DATA_OUT 0x04000000
  192. #define SCR_DT_DATA_IN 0x05000000
  193. #define SCR_MSG_OUT 0x06000000
  194. #define SCR_MSG_IN 0x07000000
  195. #define SCR_ILG_OUT 0x04000000
  196. #define SCR_ILG_IN 0x05000000
  197. /*-----------------------------------------------------------
  198. **
  199. ** Data transfer via SCSI.
  200. **
  201. **-----------------------------------------------------------
  202. **
  203. ** MOVE_ABS (LEN)
  204. ** <<start address>>
  205. **
  206. ** MOVE_IND (LEN)
  207. ** <<dnad_offset>>
  208. **
  209. ** MOVE_TBL
  210. ** <<dnad_offset>>
  211. **
  212. **-----------------------------------------------------------
  213. */
  214. #define OPC_MOVE 0x08000000
  215. #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
  216. #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
  217. #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
  218. #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
  219. #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
  220. #define SCR_CHMOV_TBL (0x10000000)
  221. /*-----------------------------------------------------------
  222. **
  223. ** Selection
  224. **
  225. **-----------------------------------------------------------
  226. **
  227. ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
  228. ** <<alternate_address>>
  229. **
  230. ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
  231. ** <<alternate_address>>
  232. **
  233. **-----------------------------------------------------------
  234. */
  235. #define SCR_SEL_ABS 0x40000000
  236. #define SCR_SEL_ABS_ATN 0x41000000
  237. #define SCR_SEL_TBL 0x42000000
  238. #define SCR_SEL_TBL_ATN 0x43000000
  239. #define SCR_JMP_REL 0x04000000
  240. #define SCR_ID(id) (((unsigned long)(id)) << 16)
  241. /*-----------------------------------------------------------
  242. **
  243. ** Waiting for Disconnect or Reselect
  244. **
  245. **-----------------------------------------------------------
  246. **
  247. ** WAIT_DISC
  248. ** dummy: <<alternate_address>>
  249. **
  250. ** WAIT_RESEL
  251. ** <<alternate_address>>
  252. **
  253. **-----------------------------------------------------------
  254. */
  255. #define SCR_WAIT_DISC 0x48000000
  256. #define SCR_WAIT_RESEL 0x50000000
  257. /*-----------------------------------------------------------
  258. **
  259. ** Bit Set / Reset
  260. **
  261. **-----------------------------------------------------------
  262. **
  263. ** SET (flags {|.. })
  264. **
  265. ** CLR (flags {|.. })
  266. **
  267. **-----------------------------------------------------------
  268. */
  269. #define SCR_SET(f) (0x58000000 | (f))
  270. #define SCR_CLR(f) (0x60000000 | (f))
  271. #define SCR_CARRY 0x00000400
  272. #define SCR_TRG 0x00000200
  273. #define SCR_ACK 0x00000040
  274. #define SCR_ATN 0x00000008
  275. /*-----------------------------------------------------------
  276. **
  277. ** Memory to memory move
  278. **
  279. **-----------------------------------------------------------
  280. **
  281. ** COPY (bytecount)
  282. ** << source_address >>
  283. ** << destination_address >>
  284. **
  285. ** SCR_COPY sets the NO FLUSH option by default.
  286. ** SCR_COPY_F does not set this option.
  287. **
  288. ** For chips which do not support this option,
  289. ** ncr_copy_and_bind() will remove this bit.
  290. **-----------------------------------------------------------
  291. */
  292. #define SCR_NO_FLUSH 0x01000000
  293. #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
  294. #define SCR_COPY_F(n) (0xc0000000 | (n))
  295. /*-----------------------------------------------------------
  296. **
  297. ** Register move and binary operations
  298. **
  299. **-----------------------------------------------------------
  300. **
  301. ** SFBR_REG (reg, op, data) reg = SFBR op data
  302. ** << 0 >>
  303. **
  304. ** REG_SFBR (reg, op, data) SFBR = reg op data
  305. ** << 0 >>
  306. **
  307. ** REG_REG (reg, op, data) reg = reg op data
  308. ** << 0 >>
  309. **
  310. **-----------------------------------------------------------
  311. ** On 810A, 860, 825A, 875, 895 and 896 chips the content
  312. ** of SFBR register can be used as data (SCR_SFBR_DATA).
  313. ** The 896 has additionnal IO registers starting at
  314. ** offset 0x80. Bit 7 of register offset is stored in
  315. ** bit 7 of the SCRIPTS instruction first DWORD.
  316. **-----------------------------------------------------------
  317. */
  318. #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */
  319. #define SCR_SFBR_REG(reg,op,data) \
  320. (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  321. #define SCR_REG_SFBR(reg,op,data) \
  322. (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  323. #define SCR_REG_REG(reg,op,data) \
  324. (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
  325. #define SCR_LOAD 0x00000000
  326. #define SCR_SHL 0x01000000
  327. #define SCR_OR 0x02000000
  328. #define SCR_XOR 0x03000000
  329. #define SCR_AND 0x04000000
  330. #define SCR_SHR 0x05000000
  331. #define SCR_ADD 0x06000000
  332. #define SCR_ADDC 0x07000000
  333. #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
  334. /*-----------------------------------------------------------
  335. **
  336. ** FROM_REG (reg) SFBR = reg
  337. ** << 0 >>
  338. **
  339. ** TO_REG (reg) reg = SFBR
  340. ** << 0 >>
  341. **
  342. ** LOAD_REG (reg, data) reg = <data>
  343. ** << 0 >>
  344. **
  345. ** LOAD_SFBR(data) SFBR = <data>
  346. ** << 0 >>
  347. **
  348. **-----------------------------------------------------------
  349. */
  350. #define SCR_FROM_REG(reg) \
  351. SCR_REG_SFBR(reg,SCR_OR,0)
  352. #define SCR_TO_REG(reg) \
  353. SCR_SFBR_REG(reg,SCR_OR,0)
  354. #define SCR_LOAD_REG(reg,data) \
  355. SCR_REG_REG(reg,SCR_LOAD,data)
  356. #define SCR_LOAD_SFBR(data) \
  357. (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
  358. /*-----------------------------------------------------------
  359. **
  360. ** LOAD from memory to register.
  361. ** STORE from register to memory.
  362. **
  363. ** Only supported by 810A, 860, 825A, 875, 895 and 896.
  364. **
  365. **-----------------------------------------------------------
  366. **
  367. ** LOAD_ABS (LEN)
  368. ** <<start address>>
  369. **
  370. ** LOAD_REL (LEN) (DSA relative)
  371. ** <<dsa_offset>>
  372. **
  373. **-----------------------------------------------------------
  374. */
  375. #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
  376. #define SCR_NO_FLUSH2 0x02000000
  377. #define SCR_DSA_REL2 0x10000000
  378. #define SCR_LOAD_R(reg, how, n) \
  379. (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  380. #define SCR_STORE_R(reg, how, n) \
  381. (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
  382. #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
  383. #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
  384. #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
  385. #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
  386. #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
  387. #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
  388. #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
  389. #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
  390. /*-----------------------------------------------------------
  391. **
  392. ** Waiting for Disconnect or Reselect
  393. **
  394. **-----------------------------------------------------------
  395. **
  396. ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
  397. ** <<address>>
  398. **
  399. ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
  400. ** <<distance>>
  401. **
  402. ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
  403. ** <<address>>
  404. **
  405. ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
  406. ** <<distance>>
  407. **
  408. ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
  409. ** <<dummy>>
  410. **
  411. ** INT [ | IFTRUE/IFFALSE ( ... ) ]
  412. ** <<ident>>
  413. **
  414. ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
  415. ** <<ident>>
  416. **
  417. ** Conditions:
  418. ** WHEN (phase)
  419. ** IF (phase)
  420. ** CARRYSET
  421. ** DATA (data, mask)
  422. **
  423. **-----------------------------------------------------------
  424. */
  425. #define SCR_NO_OP 0x80000000
  426. #define SCR_JUMP 0x80080000
  427. #define SCR_JUMP64 0x80480000
  428. #define SCR_JUMPR 0x80880000
  429. #define SCR_CALL 0x88080000
  430. #define SCR_CALLR 0x88880000
  431. #define SCR_RETURN 0x90080000
  432. #define SCR_INT 0x98080000
  433. #define SCR_INT_FLY 0x98180000
  434. #define IFFALSE(arg) (0x00080000 | (arg))
  435. #define IFTRUE(arg) (0x00000000 | (arg))
  436. #define WHEN(phase) (0x00030000 | (phase))
  437. #define IF(phase) (0x00020000 | (phase))
  438. #define DATA(D) (0x00040000 | ((D) & 0xff))
  439. #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
  440. #define CARRYSET (0x00200000)
  441. #define SIR_COMPLETE 0x10000000
  442. /* script errors */
  443. #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001
  444. #define SIR_CMD_OUT_ILL_PH 0x00000002
  445. #define SIR_STATUS_ILL_PH 0x00000003
  446. #define SIR_MSG_RECEIVED 0x00000004
  447. #define SIR_DATA_IN_ERR 0x00000005
  448. #define SIR_DATA_OUT_ERR 0x00000006
  449. #define SIR_SCRIPT_ERROR 0x00000007
  450. #define SIR_MSG_OUT_NO_CMD 0x00000008
  451. #define SIR_MSG_OVER7 0x00000009
  452. /* Fly interrupt */
  453. #define INT_ON_FY 0x00000080
  454. /* Hardware errors are defined in scsi.h */
  455. #define SCSI_IDENTIFY 0xC0
  456. #endif