stm32_rcc.h 2.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2017
  4. * Author(s): Patrice CHOTARD, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #ifndef __STM32_RCC_H_
  7. #define __STM32_RCC_H_
  8. #define AHB_PSC_1 0
  9. #define AHB_PSC_2 0x8
  10. #define AHB_PSC_4 0x9
  11. #define AHB_PSC_8 0xA
  12. #define AHB_PSC_16 0xB
  13. #define AHB_PSC_64 0xC
  14. #define AHB_PSC_128 0xD
  15. #define AHB_PSC_256 0xE
  16. #define AHB_PSC_512 0xF
  17. #define APB_PSC_1 0
  18. #define APB_PSC_2 0x4
  19. #define APB_PSC_4 0x5
  20. #define APB_PSC_8 0x6
  21. #define APB_PSC_16 0x7
  22. struct pll_psc {
  23. u8 pll_m;
  24. u16 pll_n;
  25. u8 pll_p;
  26. u8 pll_q;
  27. u8 ahb_psc;
  28. u8 apb1_psc;
  29. u8 apb2_psc;
  30. };
  31. struct stm32_clk_info {
  32. struct pll_psc sys_pll_psc;
  33. bool has_overdrive;
  34. bool v2;
  35. };
  36. enum soc_family {
  37. STM32F42X,
  38. STM32F469,
  39. STM32F7,
  40. STM32MP1,
  41. };
  42. enum apb {
  43. APB1,
  44. APB2,
  45. };
  46. struct stm32_rcc_clk {
  47. char *drv_name;
  48. enum soc_family soc;
  49. };
  50. struct stm32_rcc_regs {
  51. u32 cr; /* RCC clock control */
  52. u32 pllcfgr; /* RCC PLL configuration */
  53. u32 cfgr; /* RCC clock configuration */
  54. u32 cir; /* RCC clock interrupt */
  55. u32 ahb1rstr; /* RCC AHB1 peripheral reset */
  56. u32 ahb2rstr; /* RCC AHB2 peripheral reset */
  57. u32 ahb3rstr; /* RCC AHB3 peripheral reset */
  58. u32 rsv0;
  59. u32 apb1rstr; /* RCC APB1 peripheral reset */
  60. u32 apb2rstr; /* RCC APB2 peripheral reset */
  61. u32 rsv1[2];
  62. u32 ahb1enr; /* RCC AHB1 peripheral clock enable */
  63. u32 ahb2enr; /* RCC AHB2 peripheral clock enable */
  64. u32 ahb3enr; /* RCC AHB3 peripheral clock enable */
  65. u32 rsv2;
  66. u32 apb1enr; /* RCC APB1 peripheral clock enable */
  67. u32 apb2enr; /* RCC APB2 peripheral clock enable */
  68. u32 rsv3[2];
  69. u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */
  70. u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */
  71. u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */
  72. u32 rsv4;
  73. u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */
  74. u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */
  75. u32 rsv5[2];
  76. u32 bdcr; /* RCC Backup domain control */
  77. u32 csr; /* RCC clock control & status */
  78. u32 rsv6[2];
  79. u32 sscgr; /* RCC spread spectrum clock generation */
  80. u32 plli2scfgr; /* RCC PLLI2S configuration */
  81. /* below registers are only available on STM32F46x and STM32F7 SoCs*/
  82. u32 pllsaicfgr; /* PLLSAI configuration */
  83. u32 dckcfgr; /* dedicated clocks configuration register */
  84. /* Below registers are only available on STM32F7 SoCs */
  85. u32 dckcfgr2; /* dedicated clocks configuration register */
  86. };
  87. #endif /* __STM32_RCC_H_ */