tps65910_pmic.h 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
  4. */
  5. #ifndef __TPS65910_PMIC_H_
  6. #define __TPS65910_PMIC_H_
  7. #define TPS65910_I2C_SEL_MASK (0x1 << 4)
  8. #define TPS65910_VDD_SR_MASK (0x1 << 7)
  9. #define TPS65910_GAIN_SEL_MASK (0x3 << 6)
  10. #define TPS65910_VDD_SEL_MASK 0x7f
  11. #define TPS65910_VDD_SEL_MIN 3
  12. #define TPS65910_VDD_SEL_MAX 75
  13. #define TPS65910_SEL_MASK (0x3 << 2)
  14. #define TPS65910_SUPPLY_STATE_MASK 0x3
  15. #define TPS65910_SUPPLY_STATE_OFF 0x0
  16. #define TPS65910_SUPPLY_STATE_ON 0x1
  17. /* i2c registers */
  18. enum {
  19. TPS65910_REG_RTC_SEC = 0x00,
  20. TPS65910_REG_RTC_MIN,
  21. TPS65910_REG_RTC_HOUR,
  22. TPS65910_REG_RTC_DAY,
  23. TPS65910_REG_RTC_MONTH,
  24. TPS65910_REG_RTC_YEAR,
  25. TPS65910_REG_RTC_WEEK,
  26. TPS65910_REG_RTC_ALARM_SEC = 0x08,
  27. TPS65910_REG_RTC_ALARM_MIN,
  28. TPS65910_REG_RTC_ALARM_HOUR,
  29. TPS65910_REG_RTC_ALARM_DAY,
  30. TPS65910_REG_RTC_ALARM_MONTH,
  31. TPS65910_REG_RTC_ALARM_YEAR,
  32. TPS65910_REG_RTC_CTRL = 0x10,
  33. TPS65910_REG_RTC_STAT,
  34. TPS65910_REG_RTC_INT,
  35. TPS65910_REG_RTC_COMP_LSB,
  36. TPS65910_REG_RTC_COMP_MSB,
  37. TPS65910_REG_RTC_RESISTOR_PRG,
  38. TPS65910_REG_RTC_RESET_STAT,
  39. TPS65910_REG_BACKUP1,
  40. TPS65910_REG_BACKUP2,
  41. TPS65910_REG_BACKUP3,
  42. TPS65910_REG_BACKUP4,
  43. TPS65910_REG_BACKUP5,
  44. TPS65910_REG_PUADEN,
  45. TPS65910_REG_REF,
  46. TPS65910_REG_VRTC,
  47. TPS65910_REG_VIO = 0x20,
  48. TPS65910_REG_VDD1,
  49. TPS65910_REG_VDD1_VAL,
  50. TPS65910_REG_VDD1_VAL_SR,
  51. TPS65910_REG_VDD2,
  52. TPS65910_REG_VDD2_VAL,
  53. TPS65910_REG_VDD2_VAL_SR,
  54. TPS65910_REG_VDD3,
  55. TPS65910_REG_VDIG1 = 0x30,
  56. TPS65910_REG_VDIG2,
  57. TPS65910_REG_VAUX1,
  58. TPS65910_REG_VAUX2,
  59. TPS65910_REG_VAUX33,
  60. TPS65910_REG_VMMC,
  61. TPS65910_REG_VPLL,
  62. TPS65910_REG_VDAC,
  63. TPS65910_REG_THERM,
  64. TPS65910_REG_BATTERY_BACKUP_CHARGE,
  65. TPS65910_REG_DCDC_CTRL = 0x3e,
  66. TPS65910_REG_DEVICE_CTRL,
  67. TPS65910_REG_DEVICE_CTRL2,
  68. TPS65910_REG_SLEEP_KEEP_LDO_ON,
  69. TPS65910_REG_SLEEP_KEEP_RES_ON,
  70. TPS65910_REG_SLEEP_SET_LDO_OFF,
  71. TPS65910_REG_SLEEP_SET_RES_OFF,
  72. TPS65910_REG_EN1_LDO_ASS,
  73. TPS65910_REG_EM1_SMPS_ASS,
  74. TPS65910_REG_EN2_LDO_ASS,
  75. TPS65910_REG_EM2_SMPS_ASS,
  76. TPS65910_REG_INT_STAT = 0x50,
  77. TPS65910_REG_INT_MASK,
  78. TPS65910_REG_INT_STAT2,
  79. TPS65910_REG_INT_MASK2,
  80. TPS65910_REG_GPIO = 0x60,
  81. TPS65910_REG_JTAGREVNUM = 0x80,
  82. TPS65910_NUM_REGS
  83. };
  84. /* chip supplies */
  85. enum {
  86. TPS65910_SUPPLY_VCCIO = 0x00,
  87. TPS65910_SUPPLY_VCC1,
  88. TPS65910_SUPPLY_VCC2,
  89. TPS65910_SUPPLY_VCC3,
  90. TPS65910_SUPPLY_VCC4,
  91. TPS65910_SUPPLY_VCC5,
  92. TPS65910_SUPPLY_VCC6,
  93. TPS65910_SUPPLY_VCC7,
  94. TPS65910_NUM_SUPPLIES
  95. };
  96. /* regulator unit numbers */
  97. enum {
  98. TPS65910_UNIT_VRTC = 0x00,
  99. TPS65910_UNIT_VIO,
  100. TPS65910_UNIT_VDD1,
  101. TPS65910_UNIT_VDD2,
  102. TPS65910_UNIT_VDD3,
  103. TPS65910_UNIT_VDIG1,
  104. TPS65910_UNIT_VDIG2,
  105. TPS65910_UNIT_VPLL,
  106. TPS65910_UNIT_VDAC,
  107. TPS65910_UNIT_VAUX1,
  108. TPS65910_UNIT_VAUX2,
  109. TPS65910_UNIT_VAUX33,
  110. TPS65910_UNIT_VMMC,
  111. };
  112. /* platform data */
  113. struct tps65910_regulator_pdata {
  114. u32 supply; /* regulator supply voltage in uV */
  115. uint unit; /* unit-address according to DT */
  116. };
  117. /* driver names */
  118. #define TPS65910_BUCK_DRIVER "tps65910_buck"
  119. #define TPS65910_BOOST_DRIVER "tps65910_boost"
  120. #define TPS65910_LDO_DRIVER "tps65910_ldo"
  121. #endif /* __TPS65910_PMIC_H_ */