stpmic1.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #ifndef __PMIC_STPMIC1_H_
  6. #define __PMIC_STPMIC1_H_
  7. #include <linux/bitops.h>
  8. #define STPMIC1_MAIN_CR 0x10
  9. #define STPMIC1_BUCKS_MRST_CR 0x18
  10. #define STPMIC1_LDOS_MRST_CR 0x1a
  11. #define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck))
  12. #define STPMIC1_REFDDR_MAIN_CR 0x24
  13. #define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo))
  14. #define STPMIC1_BST_SW_CR 0x40
  15. #define STPMIC1_NVM_SR 0xb8
  16. #define STPMIC1_NVM_CR 0xb9
  17. /* Main PMIC Control Register (MAIN_CR) */
  18. #define STPMIC1_SWOFF BIT(0)
  19. #define STPMIC1_RREQ_EN BIT(1)
  20. /* BUCKS_MRST_CR */
  21. #define STPMIC1_MRST_BUCK(buck) BIT(buck)
  22. #define STPMIC1_MRST_BUCK_DEBUG (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
  23. STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
  24. /* LDOS_MRST_CR */
  25. #define STPMIC1_MRST_LDO(ldo) BIT(ldo)
  26. #define STPMIC1_MRST_LDO_DEBUG 0
  27. /* BUCKx_MAIN_CR (x=1...4) */
  28. #define STPMIC1_BUCK_ENA BIT(0)
  29. #define STPMIC1_BUCK_PREG_MODE BIT(1)
  30. #define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2)
  31. #define STPMIC1_BUCK_VOUT_SHIFT 2
  32. #define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
  33. #define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
  34. #define STPMIC1_BUCK2_1250000V STPMIC1_BUCK_VOUT(26)
  35. #define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
  36. #define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
  37. /* REFDDR_MAIN_CR */
  38. #define STPMIC1_VREF_ENA BIT(0)
  39. /* LDOX_MAIN_CR */
  40. #define STPMIC1_LDO_ENA BIT(0)
  41. #define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2)
  42. #define STPMIC1_LDO12356_VOUT_SHIFT 2
  43. #define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
  44. #define STPMIC1_LDO3_MODE BIT(7)
  45. #define STPMIC1_LDO3_DDR_SEL 31
  46. #define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9)
  47. #define STPMIC1_LDO4_UV 3300000
  48. /* BST_SW_CR */
  49. #define STPMIC1_BST_ON BIT(0)
  50. #define STPMIC1_VBUSOTG_ON BIT(1)
  51. #define STPMIC1_SWOUT_ON BIT(2)
  52. #define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
  53. /* NVM_SR */
  54. #define STPMIC1_NVM_BUSY BIT(0)
  55. /* NVM_CR */
  56. #define STPMIC1_NVM_CMD_PROGRAM 1
  57. #define STPMIC1_NVM_CMD_READ 2
  58. /* Timeout */
  59. #define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
  60. #define STPMIC1_DEFAULT_STOP_DELAY_MS 5
  61. #define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
  62. enum {
  63. STPMIC1_BUCK1,
  64. STPMIC1_BUCK2,
  65. STPMIC1_BUCK3,
  66. STPMIC1_BUCK4,
  67. STPMIC1_MAX_BUCK,
  68. };
  69. enum {
  70. STPMIC1_PREG_MODE_HP,
  71. STPMIC1_PREG_MODE_LP,
  72. };
  73. enum {
  74. STPMIC1_LDO1,
  75. STPMIC1_LDO2,
  76. STPMIC1_LDO3,
  77. STPMIC1_LDO4,
  78. STPMIC1_LDO5,
  79. STPMIC1_LDO6,
  80. STPMIC1_MAX_LDO,
  81. };
  82. enum {
  83. STPMIC1_LDO_MODE_NORMAL,
  84. STPMIC1_LDO_MODE_BYPASS,
  85. STPMIC1_LDO_MODE_SINK_SOURCE,
  86. };
  87. enum {
  88. STPMIC1_PWR_SW1,
  89. STPMIC1_PWR_SW2,
  90. STPMIC1_MAX_PWR_SW,
  91. };
  92. #endif