pci_ep.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Adapted from Linux kernel driver
  4. * Copyright (C) 2017 Texas Instruments
  5. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  6. *
  7. * (C) Copyright 2019
  8. * Ramon Fried <ramon.fried@gmail.com>
  9. */
  10. #ifndef _PCI_EP_H
  11. #define _PCI_EP_H
  12. #include <pci.h>
  13. /**
  14. * enum pci_interrupt_pin - PCI INTx interrupt values
  15. * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
  16. * @PCI_INTERRUPT_INTA: PCI INTA pin
  17. * @PCI_INTERRUPT_INTB: PCI INTB pin
  18. * @PCI_INTERRUPT_INTC: PCI INTC pin
  19. * @PCI_INTERRUPT_INTD: PCI INTD pin
  20. *
  21. * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
  22. * PCI_INTERRUPT_PIN register.
  23. */
  24. enum pci_interrupt_pin {
  25. PCI_INTERRUPT_UNKNOWN,
  26. PCI_INTERRUPT_INTA,
  27. PCI_INTERRUPT_INTB,
  28. PCI_INTERRUPT_INTC,
  29. PCI_INTERRUPT_INTD,
  30. };
  31. enum pci_barno {
  32. BAR_0,
  33. BAR_1,
  34. BAR_2,
  35. BAR_3,
  36. BAR_4,
  37. BAR_5,
  38. };
  39. enum pci_ep_irq_type {
  40. PCI_EP_IRQ_UNKNOWN,
  41. PCI_EP_IRQ_LEGACY,
  42. PCI_EP_IRQ_MSI,
  43. PCI_EP_IRQ_MSIX,
  44. };
  45. /**
  46. * struct pci_bar - represents the BAR (Base Address Register) of EP device
  47. * @phys_addr: physical address that should be mapped to the BAR
  48. * @size: the size of the address space present in BAR
  49. * pci_barno: number of pci BAR to set (0..5)
  50. * @flags: BAR access flags
  51. */
  52. struct pci_bar {
  53. dma_addr_t phys_addr;
  54. size_t size;
  55. enum pci_barno barno;
  56. int flags;
  57. };
  58. /**
  59. * struct pci_ep_header - represents standard configuration header
  60. * @vendorid: identifies device manufacturer
  61. * @deviceid: identifies a particular device
  62. * @revid: specifies a device-specific revision identifier
  63. * @progif_code: identifies a specific register-level programming interface
  64. * @subclass_code: identifies more specifically the function of the device
  65. * @baseclass_code: broadly classifies the type of function the device performs
  66. * @cache_line_size: specifies the system cacheline size in units of DWORDs
  67. * @subsys_vendor_id: vendor of the add-in card or subsystem
  68. * @subsys_id: id specific to vendor
  69. * @interrupt_pin: interrupt pin the device (or device function) uses
  70. */
  71. struct pci_ep_header {
  72. u16 vendorid;
  73. u16 deviceid;
  74. u8 revid;
  75. u8 progif_code;
  76. u8 subclass_code;
  77. u8 baseclass_code;
  78. u8 cache_line_size;
  79. u16 subsys_vendor_id;
  80. u16 subsys_id;
  81. enum pci_interrupt_pin interrupt_pin;
  82. };
  83. /* PCI endpoint operations */
  84. struct pci_ep_ops {
  85. /**
  86. * write_header() - Write a PCI configuration space header
  87. *
  88. * @dev: device to write to
  89. * @func_num: EP function to fill
  90. * @hdr: header to write
  91. * @return 0 if OK, -ve on error
  92. */
  93. int (*write_header)(struct udevice *dev, uint func_num,
  94. struct pci_ep_header *hdr);
  95. /**
  96. * read_header() - Read a PCI configuration space header
  97. *
  98. * @dev: device to write to
  99. * @func_num: EP function to fill
  100. * @hdr: header to read to
  101. * @return 0 if OK, -ve on error
  102. */
  103. int (*read_header)(struct udevice *dev, uint func_num,
  104. struct pci_ep_header *hdr);
  105. /**
  106. * set_bar() - Set BAR (Base Address Register) properties
  107. *
  108. * @dev: device to set
  109. * @func_num: EP function to set
  110. * @bar: bar data
  111. * @return 0 if OK, -ve on error
  112. */
  113. int (*set_bar)(struct udevice *dev, uint func_num,
  114. struct pci_bar *bar);
  115. /**
  116. * read_bar() - Read BAR (Base Address Register) properties
  117. *
  118. * @dev: device to read
  119. * @func_num: EP function to read
  120. * @bar: struct to copy data to
  121. * @barno: bar number to read
  122. * @return 0 if OK, -ve on error
  123. */
  124. int (*read_bar)(struct udevice *dev, uint func_num,
  125. struct pci_bar *bar, enum pci_barno barno);
  126. /**
  127. * clear_bar() - clear BAR (Base Address Register)
  128. *
  129. * @dev: device to clear
  130. * @func_num: EP function to clear
  131. * @bar: bar number
  132. * @return 0 if OK, -ve on error
  133. */
  134. int (*clear_bar)(struct udevice *dev, uint func_num,
  135. enum pci_barno bar);
  136. /**
  137. * map_addr() - map CPU address to PCI address
  138. *
  139. * outband region is used in order to generate PCI read/write
  140. * transaction from local memory/write.
  141. *
  142. * @dev: device to set
  143. * @func_num: EP function to set
  144. * @addr: local physical address base
  145. * @pci_addr: pci address to translate to
  146. * @size: region size
  147. * @return 0 if OK, -ve on error
  148. */
  149. int (*map_addr)(struct udevice *dev, uint func_num,
  150. phys_addr_t addr, u64 pci_addr, size_t size);
  151. /**
  152. * unmap_addr() - unmap CPU address to PCI address
  153. *
  154. * unmap previously mapped region.
  155. *
  156. * @dev: device to set
  157. * @func_num: EP function to set
  158. * @addr: local physical address base
  159. * @return 0 if OK, -ve on error
  160. */
  161. int (*unmap_addr)(struct udevice *dev, uint func_num,
  162. phys_addr_t addr);
  163. /**
  164. * set_msi() - set msi capability property
  165. *
  166. * set the number of required MSI vectors the device
  167. * needs for operation.
  168. *
  169. * @dev: device to set
  170. * @func_num: EP function to set
  171. * @interrupts: required interrupts count
  172. * @return 0 if OK, -ve on error
  173. */
  174. int (*set_msi)(struct udevice *dev, uint func_num, uint interrupts);
  175. /**
  176. * get_msi() - get the number of MSI interrupts allocated by the host.
  177. *
  178. * Read the Multiple Message Enable bitfield from
  179. * Message control register.
  180. *
  181. * @dev: device to use
  182. * @func_num: EP function to use
  183. * @return msi count if OK, -EINVAL if msi were not enabled at host.
  184. */
  185. int (*get_msi)(struct udevice *dev, uint func_num);
  186. /**
  187. * set_msix() - set msix capability property
  188. *
  189. * set the number of required MSIx vectors the device
  190. * needs for operation.
  191. *
  192. * @dev: device to set
  193. * @func_num: EP function to set
  194. * @interrupts: required interrupts count
  195. * @return 0 if OK, -ve on error
  196. */
  197. int (*set_msix)(struct udevice *dev, uint func_num,
  198. uint interrupts);
  199. /**
  200. * get_msix() - get the number of MSIx interrupts allocated by the host.
  201. *
  202. * Read the Multiple Message Enable bitfield from
  203. * Message control register.
  204. *
  205. * @dev: device to use
  206. * @func_num: EP function to use
  207. * @return msi count if OK, -EINVAL if msi were not enabled at host.
  208. */
  209. int (*get_msix)(struct udevice *dev, uint func_num);
  210. /**
  211. * raise_irq() - raise a legacy, MSI or MSI-X interrupt
  212. *
  213. * @dev: device to set
  214. * @func_num: EP function to set
  215. * @type: type of irq to send
  216. * @interrupt_num: interrupt vector to use
  217. * @return 0 if OK, -ve on error
  218. */
  219. int (*raise_irq)(struct udevice *dev, uint func_num,
  220. enum pci_ep_irq_type type, uint interrupt_num);
  221. /**
  222. * start() - start the PCI link
  223. *
  224. * @dev: device to set
  225. * @return 0 if OK, -ve on error
  226. */
  227. int (*start)(struct udevice *dev);
  228. /**
  229. * stop() - stop the PCI link
  230. *
  231. * @dev: device to set
  232. * @return 0 if OK, -ve on error
  233. */
  234. int (*stop)(struct udevice *dev);
  235. };
  236. #define pci_ep_get_ops(dev) ((struct pci_ep_ops *)(dev)->driver->ops)
  237. /**
  238. * pci_ep_write_header() - Write a PCI configuration space header
  239. *
  240. * @dev: device to write to
  241. * @func_num: EP function to fill
  242. * @hdr: header to write
  243. * @return 0 if OK, -ve on error
  244. */
  245. int pci_ep_write_header(struct udevice *dev, uint func_num,
  246. struct pci_ep_header *hdr);
  247. /**
  248. * dm_pci_ep_read_header() - Read a PCI configuration space header
  249. *
  250. * @dev: device to write to
  251. * @func_num: EP function to fill
  252. * @hdr: header to read to
  253. * @return 0 if OK, -ve on error
  254. */
  255. int pci_ep_read_header(struct udevice *dev, uint func_num,
  256. struct pci_ep_header *hdr);
  257. /**
  258. * pci_ep_set_bar() - Set BAR (Base Address Register) properties
  259. *
  260. * @dev: device to set
  261. * @func_num: EP function to set
  262. * @bar: bar data
  263. * @return 0 if OK, -ve on error
  264. */
  265. int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar);
  266. /**
  267. * pci_ep_read_bar() - Read BAR (Base Address Register) properties
  268. *
  269. * @dev: device to read
  270. * @func_num: EP function to read
  271. * @bar: struct to copy data to
  272. * @barno: bar number to read
  273. * @return 0 if OK, -ve on error
  274. */
  275. int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
  276. enum pci_barno barno);
  277. /**
  278. * pci_ep_clear_bar() - Clear BAR (Base Address Register)
  279. * mark the BAR as empty so host won't map it.
  280. * @dev: device to clear
  281. * @func_num: EP function to clear
  282. * @bar: bar number
  283. * @return 0 if OK, -ve on error
  284. */
  285. int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar);
  286. /**
  287. * pci_ep_map_addr() - map CPU address to PCI address
  288. *
  289. * outband region is used in order to generate PCI read/write
  290. * transaction from local memory/write.
  291. *
  292. * @dev: device to set
  293. * @func_num: EP function to set
  294. * @addr: local physical address base
  295. * @pci_addr: pci address to translate to
  296. * @size: region size
  297. * @return 0 if OK, -ve on error
  298. */
  299. int pci_ep_map_addr(struct udevice *dev, uint func_num, phys_addr_t addr,
  300. u64 pci_addr, size_t size);
  301. /**
  302. * pci_ep_unmap_addr() - unmap CPU address to PCI address
  303. *
  304. * unmap previously mapped region.
  305. *
  306. * @dev: device to set
  307. * @func_num: EP function to set
  308. * @addr: local physical address base
  309. * @return 0 if OK, -ve on error
  310. */
  311. int pci_ep_unmap_addr(struct udevice *dev, uint func_num, phys_addr_t addr);
  312. /**
  313. * pci_ep_set_msi() - set msi capability property
  314. *
  315. * set the number of required MSI vectors the device
  316. * needs for operation.
  317. *
  318. * @dev: device to set
  319. * @func_num: EP function to set
  320. * @interrupts: required interrupts count
  321. * @return 0 if OK, -ve on error
  322. */
  323. int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts);
  324. /**
  325. * pci_ep_get_msi() - get the number of MSI interrupts allocated by the host.
  326. *
  327. * Read the Multiple Message Enable bitfield from
  328. * Message control register.
  329. *
  330. * @dev: device to use
  331. * @func_num: EP function to use
  332. * @return msi count if OK, -EINVAL if msi were not enabled at host.
  333. */
  334. int pci_ep_get_msi(struct udevice *dev, uint func_num);
  335. /**
  336. * pci_ep_set_msix() - set msi capability property
  337. *
  338. * set the number of required MSIx vectors the device
  339. * needs for operation.
  340. *
  341. * @dev: device to set
  342. * @func_num: EP function to set
  343. * @interrupts: required interrupts count
  344. * @return 0 if OK, -ve on error
  345. */
  346. int pci_ep_set_msix(struct udevice *dev, uint func_num, uint interrupts);
  347. /**
  348. * pci_ep_get_msix() - get the number of MSIx interrupts allocated by the host.
  349. *
  350. * Read the Multiple Message Enable bitfield from
  351. * Message control register.
  352. *
  353. * @dev: device to use
  354. * @func_num: EP function to use
  355. * @return msi count if OK, -EINVAL if msi were not enabled at host.
  356. */
  357. int pci_ep_get_msix(struct udevice *dev, uint func_num);
  358. /**
  359. * pci_ep_raise_irq() - raise a legacy, MSI or MSI-X interrupt
  360. *
  361. * @dev: device to set
  362. * @func_num: EP function to set
  363. * @type: type of irq to send
  364. * @interrupt_num: interrupt vector to use
  365. * @return 0 if OK, -ve on error
  366. */
  367. int pci_ep_raise_irq(struct udevice *dev, uint func_num,
  368. enum pci_ep_irq_type type, uint interrupt_num);
  369. /**
  370. * pci_ep_start() - start the PCI link
  371. *
  372. * Enable PCI endpoint device and start link
  373. * process.
  374. *
  375. * @dev: device to set
  376. * @return 0 if OK, -ve on error
  377. */
  378. int pci_ep_start(struct udevice *dev);
  379. /**
  380. * pci_ep_stop() - stop the PCI link
  381. *
  382. * Disable PCI endpoint device and stop
  383. * link.
  384. *
  385. * @dev: device to set
  386. * @return 0 if OK, -ve on error
  387. */
  388. int pci_ep_stop(struct udevice *dev);
  389. #endif