omap3_spi.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #ifndef __OMAP3_SPI_H_
  3. #define __OMAP3_SPI_H_
  4. /* per-register bitmasks */
  5. #define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
  6. #define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
  7. #define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
  8. #define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
  9. #define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0)
  10. #define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0)
  11. #define OMAP3_MCSPI_MODULCTRL_MS BIT(2)
  12. #define OMAP3_MCSPI_MODULCTRL_STEST BIT(3)
  13. #define OMAP3_MCSPI_CHCONF_PHA BIT(0)
  14. #define OMAP3_MCSPI_CHCONF_POL BIT(1)
  15. #define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2)
  16. #define OMAP3_MCSPI_CHCONF_EPOL BIT(6)
  17. #define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7)
  18. #define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
  19. #define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
  20. #define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12)
  21. #define OMAP3_MCSPI_CHCONF_DMAW BIT(14)
  22. #define OMAP3_MCSPI_CHCONF_DMAR BIT(15)
  23. #define OMAP3_MCSPI_CHCONF_DPE0 BIT(16)
  24. #define OMAP3_MCSPI_CHCONF_DPE1 BIT(17)
  25. #define OMAP3_MCSPI_CHCONF_IS BIT(18)
  26. #define OMAP3_MCSPI_CHCONF_TURBO BIT(19)
  27. #define OMAP3_MCSPI_CHCONF_FORCE BIT(20)
  28. #define OMAP3_MCSPI_CHSTAT_RXS BIT(0)
  29. #define OMAP3_MCSPI_CHSTAT_TXS BIT(1)
  30. #define OMAP3_MCSPI_CHSTAT_EOT BIT(2)
  31. #define OMAP3_MCSPI_CHCTRL_EN BIT(0)
  32. #define OMAP3_MCSPI_CHCTRL_DIS (0 << 0)
  33. #define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0)
  34. #define MCSPI_PINDIR_D0_IN_D1_OUT 0
  35. #define MCSPI_PINDIR_D0_OUT_D1_IN 1
  36. #define OMAP3_MCSPI_MAX_FREQ 48000000
  37. #define SPI_WAIT_TIMEOUT 10
  38. #define OMAP4_MCSPI_REG_OFFSET 0x100
  39. /* OMAP3 McSPI registers */
  40. struct mcspi_channel {
  41. unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */
  42. unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */
  43. unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */
  44. unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */
  45. unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */
  46. };
  47. struct mcspi {
  48. unsigned char res1[0x10];
  49. unsigned int sysconfig; /* 0x10 */
  50. unsigned int sysstatus; /* 0x14 */
  51. unsigned int irqstatus; /* 0x18 */
  52. unsigned int irqenable; /* 0x1C */
  53. unsigned int wakeupenable; /* 0x20 */
  54. unsigned int syst; /* 0x24 */
  55. unsigned int modulctrl; /* 0x28 */
  56. struct mcspi_channel channel[4];
  57. /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
  58. /* channel1: 0x40 - 0x50, bus 0 & 1 */
  59. /* channel2: 0x54 - 0x64, bus 0 & 1 */
  60. /* channel3: 0x68 - 0x78, bus 0 */
  61. };
  62. struct omap3_spi_plat {
  63. struct mcspi *regs;
  64. unsigned int pin_dir:1;
  65. };
  66. #endif