ns16550.h 8.4 KB

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  1. /*
  2. * NS16550 Serial Port
  3. * originally from linux source (arch/powerpc/boot/ns16550.h)
  4. *
  5. * Cleanup and unification
  6. * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
  7. *
  8. * modified slightly to
  9. * have addresses as offsets from CONFIG_SYS_ISA_BASE
  10. * added a few more definitions
  11. * added prototypes for ns16550.c
  12. * reduced no of com ports to 2
  13. * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
  14. *
  15. * added support for port on 64-bit bus
  16. * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
  17. */
  18. /*
  19. * Note that the following macro magic uses the fact that the compiler
  20. * will not allocate storage for arrays of size 0
  21. */
  22. #include <linux/types.h>
  23. #ifdef CONFIG_DM_SERIAL
  24. /*
  25. * For driver model we always use one byte per register, and sort out the
  26. * differences in the driver
  27. */
  28. #define CONFIG_SYS_NS16550_REG_SIZE (-1)
  29. #endif
  30. #ifdef CONFIG_NS16550_DYNAMIC
  31. #define UART_REG(x) unsigned char x
  32. #else
  33. #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
  34. #error "Please define NS16550 registers size."
  35. #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
  36. #define UART_REG(x) u32 x
  37. #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
  38. #define UART_REG(x) \
  39. unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
  40. unsigned char x;
  41. #elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
  42. #define UART_REG(x) \
  43. unsigned char x; \
  44. unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
  45. #endif
  46. #endif /* CONFIG_NS16550_DYNAMIC */
  47. enum ns16550_flags {
  48. NS16550_FLAG_IO = 1 << 0, /* Use I/O access (else mem-mapped) */
  49. NS16550_FLAG_ENDIAN = 1 << 1, /* Use out_le/be_32() */
  50. NS16550_FLAG_BE = 1 << 2, /* Big-endian access (else little) */
  51. };
  52. /**
  53. * struct ns16550_platdata - information about a NS16550 port
  54. *
  55. * @base: Base register address
  56. * @reg_width: IO accesses size of registers (in bytes, 1 or 4)
  57. * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
  58. * @reg_offset: Offset to start of registers (normally 0)
  59. * @clock: UART base clock speed in Hz
  60. * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL)
  61. * @flags: A few flags (enum ns16550_flags)
  62. * @bdf: PCI slot/function (pci_dev_t)
  63. */
  64. struct ns16550_platdata {
  65. unsigned long base;
  66. int reg_width;
  67. int reg_shift;
  68. int reg_offset;
  69. int clock;
  70. u32 fcr;
  71. int flags;
  72. #if defined(CONFIG_PCI) && defined(CONFIG_SPL)
  73. int bdf;
  74. #endif
  75. };
  76. struct udevice;
  77. struct NS16550 {
  78. UART_REG(rbr); /* 0 */
  79. UART_REG(ier); /* 1 */
  80. UART_REG(fcr); /* 2 */
  81. UART_REG(lcr); /* 3 */
  82. UART_REG(mcr); /* 4 */
  83. UART_REG(lsr); /* 5 */
  84. UART_REG(msr); /* 6 */
  85. UART_REG(spr); /* 7 */
  86. #ifdef CONFIG_SOC_DA8XX
  87. UART_REG(reg8); /* 8 */
  88. UART_REG(reg9); /* 9 */
  89. UART_REG(revid1); /* A */
  90. UART_REG(revid2); /* B */
  91. UART_REG(pwr_mgmt); /* C */
  92. UART_REG(mdr1); /* D */
  93. #else
  94. UART_REG(mdr1); /* 8 */
  95. UART_REG(reg9); /* 9 */
  96. UART_REG(regA); /* A */
  97. UART_REG(regB); /* B */
  98. UART_REG(regC); /* C */
  99. UART_REG(regD); /* D */
  100. UART_REG(regE); /* E */
  101. UART_REG(uasr); /* F */
  102. UART_REG(scr); /* 10*/
  103. UART_REG(ssr); /* 11*/
  104. #endif
  105. #ifdef CONFIG_DM_SERIAL
  106. struct ns16550_platdata *plat;
  107. #endif
  108. };
  109. #define thr rbr
  110. #define iir fcr
  111. #define dll rbr
  112. #define dlm ier
  113. typedef struct NS16550 *NS16550_t;
  114. /*
  115. * These are the definitions for the FIFO Control Register
  116. */
  117. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  118. #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
  119. #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
  120. #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
  121. #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
  122. #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
  123. #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
  124. #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
  125. #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
  126. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  127. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  128. /* Ingenic JZ47xx specific UART-enable bit. */
  129. #define UART_FCR_UME 0x10
  130. /* Clear & enable FIFOs */
  131. #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
  132. UART_FCR_RXSR | \
  133. UART_FCR_TXSR)
  134. /*
  135. * These are the definitions for the Modem Control Register
  136. */
  137. #define UART_MCR_DTR 0x01 /* DTR */
  138. #define UART_MCR_RTS 0x02 /* RTS */
  139. #define UART_MCR_OUT1 0x04 /* Out 1 */
  140. #define UART_MCR_OUT2 0x08 /* Out 2 */
  141. #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
  142. #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
  143. #define UART_MCR_DMA_EN 0x04
  144. #define UART_MCR_TX_DFR 0x08
  145. /*
  146. * These are the definitions for the Line Control Register
  147. *
  148. * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  149. * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  150. */
  151. #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
  152. #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
  153. #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
  154. #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
  155. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  156. #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
  157. #define UART_LCR_PEN 0x08 /* Parity eneble */
  158. #define UART_LCR_EPS 0x10 /* Even Parity Select */
  159. #define UART_LCR_STKP 0x20 /* Stick Parity */
  160. #define UART_LCR_SBRK 0x40 /* Set Break */
  161. #define UART_LCR_BKSE 0x80 /* Bank select enable */
  162. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  163. /*
  164. * These are the definitions for the Line Status Register
  165. */
  166. #define UART_LSR_DR 0x01 /* Data ready */
  167. #define UART_LSR_OE 0x02 /* Overrun */
  168. #define UART_LSR_PE 0x04 /* Parity error */
  169. #define UART_LSR_FE 0x08 /* Framing error */
  170. #define UART_LSR_BI 0x10 /* Break */
  171. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  172. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  173. #define UART_LSR_ERR 0x80 /* Error */
  174. #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
  175. #define UART_MSR_RI 0x40 /* Ring Indicator */
  176. #define UART_MSR_DSR 0x20 /* Data Set Ready */
  177. #define UART_MSR_CTS 0x10 /* Clear to Send */
  178. #define UART_MSR_DDCD 0x08 /* Delta DCD */
  179. #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
  180. #define UART_MSR_DDSR 0x02 /* Delta DSR */
  181. #define UART_MSR_DCTS 0x01 /* Delta CTS */
  182. /*
  183. * These are the definitions for the Interrupt Identification Register
  184. */
  185. #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
  186. #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
  187. #define UART_IIR_MSI 0x00 /* Modem status interrupt */
  188. #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
  189. #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
  190. #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
  191. /*
  192. * These are the definitions for the Interrupt Enable Register
  193. */
  194. #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
  195. #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
  196. #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
  197. #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
  198. /* useful defaults for LCR */
  199. #define UART_LCR_8N1 0x03
  200. void NS16550_init(NS16550_t com_port, int baud_divisor);
  201. void NS16550_putc(NS16550_t com_port, char c);
  202. char NS16550_getc(NS16550_t com_port);
  203. int NS16550_tstc(NS16550_t com_port);
  204. void NS16550_reinit(NS16550_t com_port, int baud_divisor);
  205. /**
  206. * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
  207. *
  208. * Given the UART input clock and required baudrate, calculate the divisor
  209. * that should be used.
  210. *
  211. * @port: UART port
  212. * @clock: UART input clock speed in Hz
  213. * @baudrate: Required baud rate
  214. * @return baud rate divisor that should be used
  215. */
  216. int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
  217. /**
  218. * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
  219. *
  220. * Decode a device tree node for an ns16550 device. This includes the
  221. * register base address and register shift properties. The caller must set
  222. * up the clock frequency.
  223. *
  224. * @dev: dev to decode platform data for
  225. * @return: 0 if OK, -EINVAL on error
  226. */
  227. int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
  228. /**
  229. * ns16550_serial_probe() - probe a serial port
  230. *
  231. * This sets up the serial port ready for use, except for the baud rate
  232. * @return 0, or -ve on error
  233. */
  234. int ns16550_serial_probe(struct udevice *dev);
  235. /**
  236. * struct ns16550_serial_ops - ns16550 serial operations
  237. *
  238. * These should be used by the client driver for the driver's 'ops' member
  239. */
  240. extern const struct dm_serial_ops ns16550_serial_ops;