mvebu_mmc.h 7.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Marvell MMC/SD/SDIO driver
  4. *
  5. * (C) Copyright 2012
  6. * Marvell Semiconductor <www.marvell.com>
  7. * Written-by: Maen Suleiman, Gerald Kerma
  8. */
  9. #ifndef __MVEBU_MMC_H__
  10. #define __MVEBU_MMC_H__
  11. /* needed for the mmc_cfg definition */
  12. #include <mmc.h>
  13. #define MMC_BLOCK_SIZE 512
  14. /*
  15. * Clock rates
  16. */
  17. #define MVEBU_MMC_CLOCKRATE_MAX 50000000
  18. #define MVEBU_MMC_BASE_DIV_MAX 0x7ff
  19. #define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK
  20. #define MVEBU_MMC_BASE_FAST_CLK_100 100000000
  21. #define MVEBU_MMC_BASE_FAST_CLK_200 200000000
  22. /* SDIO register */
  23. #define SDIO_SYS_ADDR_LOW 0x000
  24. #define SDIO_SYS_ADDR_HI 0x004
  25. #define SDIO_BLK_SIZE 0x008
  26. #define SDIO_BLK_COUNT 0x00c
  27. #define SDIO_ARG_LOW 0x010
  28. #define SDIO_ARG_HI 0x014
  29. #define SDIO_XFER_MODE 0x018
  30. #define SDIO_CMD 0x01c
  31. #define SDIO_RSP(i) (0x020 + ((i)<<2))
  32. #define SDIO_RSP0 0x020
  33. #define SDIO_RSP1 0x024
  34. #define SDIO_RSP2 0x028
  35. #define SDIO_RSP3 0x02c
  36. #define SDIO_RSP4 0x030
  37. #define SDIO_RSP5 0x034
  38. #define SDIO_RSP6 0x038
  39. #define SDIO_RSP7 0x03c
  40. #define SDIO_BUF_DATA_PORT 0x040
  41. #define SDIO_RSVED 0x044
  42. #define SDIO_HW_STATE 0x048
  43. #define SDIO_PRESENT_STATE0 0x048
  44. #define SDIO_PRESENT_STATE1 0x04c
  45. #define SDIO_HOST_CTRL 0x050
  46. #define SDIO_BLK_GAP_CTRL 0x054
  47. #define SDIO_CLK_CTRL 0x058
  48. #define SDIO_SW_RESET 0x05c
  49. #define SDIO_NOR_INTR_STATUS 0x060
  50. #define SDIO_ERR_INTR_STATUS 0x064
  51. #define SDIO_NOR_STATUS_EN 0x068
  52. #define SDIO_ERR_STATUS_EN 0x06c
  53. #define SDIO_NOR_INTR_EN 0x070
  54. #define SDIO_ERR_INTR_EN 0x074
  55. #define SDIO_AUTOCMD12_ERR_STATUS 0x078
  56. #define SDIO_CURR_BYTE_LEFT 0x07c
  57. #define SDIO_CURR_BLK_LEFT 0x080
  58. #define SDIO_AUTOCMD12_ARG_LOW 0x084
  59. #define SDIO_AUTOCMD12_ARG_HI 0x088
  60. #define SDIO_AUTOCMD12_INDEX 0x08c
  61. #define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2))
  62. #define SDIO_AUTO_RSP0 0x090
  63. #define SDIO_AUTO_RSP1 0x094
  64. #define SDIO_AUTO_RSP2 0x098
  65. #define SDIO_CLK_DIV 0x128
  66. #define WINDOW_CTRL(i) (0x108 + ((i) << 3))
  67. #define WINDOW_BASE(i) (0x10c + ((i) << 3))
  68. /* SDIO_PRESENT_STATE */
  69. #define CARD_BUSY (1 << 1)
  70. #define CMD_INHIBIT (1 << 0)
  71. #define CMD_TXACTIVE (1 << 8)
  72. #define CMD_RXACTIVE (1 << 9)
  73. #define CMD_FIFO_EMPTY (1 << 13)
  74. #define CMD_AUTOCMD12ACTIVE (1 << 14)
  75. #define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
  76. CMD_RXACTIVE | \
  77. CMD_TXACTIVE | \
  78. CMD_INHIBIT | \
  79. CARD_BUSY)
  80. /*
  81. * SDIO_CMD
  82. */
  83. #define SDIO_CMD_RSP_NONE (0 << 0)
  84. #define SDIO_CMD_RSP_136 (1 << 0)
  85. #define SDIO_CMD_RSP_48 (2 << 0)
  86. #define SDIO_CMD_RSP_48BUSY (3 << 0)
  87. #define SDIO_CMD_CHECK_DATACRC16 (1 << 2)
  88. #define SDIO_CMD_CHECK_CMDCRC (1 << 3)
  89. #define SDIO_CMD_INDX_CHECK (1 << 4)
  90. #define SDIO_CMD_DATA_PRESENT (1 << 5)
  91. #define SDIO_UNEXPECTED_RESP (1 << 7)
  92. #define SDIO_CMD_INDEX(x) ((x) << 8)
  93. /*
  94. * SDIO_XFER_MODE
  95. */
  96. #define SDIO_XFER_MODE_STOP_CLK (1 << 5)
  97. #define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1)
  98. #define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2)
  99. #define SDIO_XFER_MODE_INT_CHK_EN (1 << 3)
  100. #define SDIO_XFER_MODE_TO_HOST (1 << 4)
  101. #define SDIO_XFER_MODE_DMA (0 << 6)
  102. /*
  103. * SDIO_HOST_CTRL
  104. */
  105. #define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0)
  106. #define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1)
  107. #define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1)
  108. #define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1)
  109. #define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1)
  110. #define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1)
  111. #define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3)
  112. #define SDIO_HOST_CTRL_LSB_FIRST (1 << 4)
  113. #define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9)
  114. #define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9)
  115. #define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10)
  116. #define SDIO_HOST_CTRL_TMOUT_MAX 0xf
  117. #define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11)
  118. #define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11)
  119. #define SDIO_HOST_CTRL_TMOUT_EN (1 << 15)
  120. /*
  121. * SDIO_SW_RESET
  122. */
  123. #define SDIO_SW_RESET_NOW (1 << 8)
  124. /*
  125. * Normal interrupt status bits
  126. */
  127. #define SDIO_NOR_ERROR (1 << 15)
  128. #define SDIO_NOR_UNEXP_RSP (1 << 14)
  129. #define SDIO_NOR_AUTOCMD12_DONE (1 << 13)
  130. #define SDIO_NOR_SUSPEND_ON (1 << 12)
  131. #define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11)
  132. #define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10)
  133. #define SDIO_NOR_READ_WAIT_ON (1 << 9)
  134. #define SDIO_NOR_CARD_INT (1 << 8)
  135. #define SDIO_NOR_READ_READY (1 << 5)
  136. #define SDIO_NOR_WRITE_READY (1 << 4)
  137. #define SDIO_NOR_DMA_INI (1 << 3)
  138. #define SDIO_NOR_BLK_GAP_EVT (1 << 2)
  139. #define SDIO_NOR_XFER_DONE (1 << 1)
  140. #define SDIO_NOR_CMD_DONE (1 << 0)
  141. /*
  142. * Error status bits
  143. */
  144. #define SDIO_ERR_CRC_STATUS (1 << 14)
  145. #define SDIO_ERR_CRC_STARTBIT (1 << 13)
  146. #define SDIO_ERR_CRC_ENDBIT (1 << 12)
  147. #define SDIO_ERR_RESP_TBIT (1 << 11)
  148. #define SDIO_ERR_XFER_SIZE (1 << 10)
  149. #define SDIO_ERR_CMD_STARTBIT (1 << 9)
  150. #define SDIO_ERR_AUTOCMD12 (1 << 8)
  151. #define SDIO_ERR_DATA_ENDBIT (1 << 6)
  152. #define SDIO_ERR_DATA_CRC (1 << 5)
  153. #define SDIO_ERR_DATA_TIMEOUT (1 << 4)
  154. #define SDIO_ERR_CMD_INDEX (1 << 3)
  155. #define SDIO_ERR_CMD_ENDBIT (1 << 2)
  156. #define SDIO_ERR_CMD_CRC (1 << 1)
  157. #define SDIO_ERR_CMD_TIMEOUT (1 << 0)
  158. /* enable all for polling */
  159. #define SDIO_POLL_MASK 0xffff
  160. /*
  161. * CMD12 error status bits
  162. */
  163. #define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0)
  164. #define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1)
  165. #define SDIO_AUTOCMD12_ERR_CRC (1 << 2)
  166. #define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3)
  167. #define SDIO_AUTOCMD12_ERR_INDEX (1 << 4)
  168. #define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5)
  169. #define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6)
  170. #define MMC_RSP_PRESENT (1 << 0)
  171. /* 136 bit response */
  172. #define MMC_RSP_136 (1 << 1)
  173. /* expect valid crc */
  174. #define MMC_RSP_CRC (1 << 2)
  175. /* card may send busy */
  176. #define MMC_RSP_BUSY (1 << 3)
  177. /* response contains opcode */
  178. #define MMC_RSP_OPCODE (1 << 4)
  179. #define MMC_BUSMODE_OPENDRAIN 1
  180. #define MMC_BUSMODE_PUSHPULL 2
  181. #define MMC_BUS_WIDTH_1 0
  182. #define MMC_BUS_WIDTH_4 2
  183. #define MMC_BUS_WIDTH_8 3
  184. /* Can the host do 4 bit transfers */
  185. #define MMC_CAP_4_BIT_DATA (1 << 0)
  186. /* Can do MMC high-speed timing */
  187. #define MMC_CAP_MMC_HIGHSPEED (1 << 1)
  188. /* Can do SD high-speed timing */
  189. #define MMC_CAP_SD_HIGHSPEED (1 << 2)
  190. /* Can signal pending SDIO IRQs */
  191. #define MMC_CAP_SDIO_IRQ (1 << 3)
  192. /* Talks only SPI protocols */
  193. #define MMC_CAP_SPI (1 << 4)
  194. /* Can the host do 8 bit transfers */
  195. #define MMC_CAP_8_BIT_DATA (1 << 6)
  196. /* Waits while card is busy */
  197. #define MMC_CAP_WAIT_WHILE_BUSY (1 << 9)
  198. /* Allow erase/trim commands */
  199. #define MMC_CAP_ERASE (1 << 10)
  200. /* can support DDR mode at 1.8V */
  201. #define MMC_CAP_1_8V_DDR (1 << 11)
  202. /* can support DDR mode at 1.2V */
  203. #define MMC_CAP_1_2V_DDR (1 << 12)
  204. /* Can power off after boot */
  205. #define MMC_CAP_POWER_OFF_CARD (1 << 13)
  206. /* CMD14/CMD19 bus width ok */
  207. #define MMC_CAP_BUS_WIDTH_TEST (1 << 14)
  208. /* Host supports UHS SDR12 mode */
  209. #define MMC_CAP_UHS_SDR12 (1 << 15)
  210. /* Host supports UHS SDR25 mode */
  211. #define MMC_CAP_UHS_SDR25 (1 << 16)
  212. /* Host supports UHS SDR50 mode */
  213. #define MMC_CAP_UHS_SDR50 (1 << 17)
  214. /* Host supports UHS SDR104 mode */
  215. #define MMC_CAP_UHS_SDR104 (1 << 18)
  216. /* Host supports UHS DDR50 mode */
  217. #define MMC_CAP_UHS_DDR50 (1 << 19)
  218. /* Host supports Driver Type A */
  219. #define MMC_CAP_DRIVER_TYPE_A (1 << 23)
  220. /* Host supports Driver Type C */
  221. #define MMC_CAP_DRIVER_TYPE_C (1 << 24)
  222. /* Host supports Driver Type D */
  223. #define MMC_CAP_DRIVER_TYPE_D (1 << 25)
  224. /* CMD23 supported. */
  225. #define MMC_CAP_CMD23 (1 << 30)
  226. /* Hardware reset */
  227. #define MMC_CAP_HW_RESET (1 << 31)
  228. struct mvebu_mmc_cfg {
  229. u32 mvebu_mmc_base;
  230. u32 mvebu_mmc_clk;
  231. u8 max_bus_width;
  232. struct mmc_config cfg;
  233. };
  234. /*
  235. * Functions prototypes
  236. */
  237. int mvebu_mmc_init(struct bd_info *bis);
  238. #endif /* __MVEBU_MMC_H__ */