mpc86xx.h 2.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990
  1. /*
  2. * Copyright 2006 Freescale Semiconductor.
  3. * Jeffrey Brown
  4. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  5. */
  6. #ifndef __MPC86xx_H__
  7. #define __MPC86xx_H__
  8. #include <asm/fsl_lbc.h>
  9. #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
  10. #define _START_OFFSET EXC_OFF_SYS_RESET
  11. /*
  12. * platform register addresses
  13. */
  14. #define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4)
  15. #define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000)
  16. #define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008)
  17. /*
  18. * l2cr values. Look in config_<BOARD>.h for the actual setup
  19. */
  20. #define l2cr 1017
  21. #define L2CR_L2E 0x80000000 /* bit 0 - enable */
  22. #define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
  23. #define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
  24. #define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
  25. #define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
  26. #define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
  27. #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
  28. #define L2CR_L2IP 0x00000001 /* global invalidate in progress */
  29. #define HID0_XBSEN 0x00000100
  30. #define HID0_HIGH_BAT_EN 0x00800000
  31. #define HID0_XAEN 0x00020000
  32. #ifndef __ASSEMBLY__
  33. typedef struct {
  34. unsigned long freq_processor;
  35. unsigned long freq_systembus;
  36. unsigned long freq_localbus;
  37. } MPC86xx_SYS_INFO;
  38. #define l1icache_enable icache_enable
  39. void l2cache_enable(void);
  40. void l1dcache_enable(void);
  41. static __inline__ unsigned long get_hid0 (void)
  42. {
  43. unsigned long hid0;
  44. asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
  45. return hid0;
  46. }
  47. static __inline__ unsigned long get_hid1 (void)
  48. {
  49. unsigned long hid1;
  50. asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
  51. return hid1;
  52. }
  53. static __inline__ void set_hid0 (unsigned long hid0)
  54. {
  55. asm volatile("mtspr 1008, %0" : : "r" (hid0));
  56. }
  57. static __inline__ void set_hid1 (unsigned long hid1)
  58. {
  59. asm volatile("mtspr 1009, %0" : : "r" (hid1));
  60. }
  61. static __inline__ unsigned long get_l2cr (void)
  62. {
  63. unsigned long l2cr_val;
  64. asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
  65. return l2cr_val;
  66. }
  67. void setup_ddr_bat(phys_addr_t dram_size);
  68. extern void setup_bats(void);
  69. #endif /* _ASMLANGUAGE */
  70. #endif /* __MPC86xx_H__ */