mpc106.h 4.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. */
  6. #ifndef _MPC106_PCI_H
  7. #define _MPC106_PCI_H
  8. /*
  9. * Defines for the MPC106 PCI Config address and data registers followed by
  10. * defines for the standard PCI device configuration header.
  11. */
  12. #define PCIDEVID_MPC106 0x0
  13. /*
  14. * MPC106 Registers
  15. */
  16. #define MPC106_REG 0x80000000
  17. #ifdef CONFIG_SYS_ADDRESS_MAP_A
  18. #define MPC106_REG_ADDR 0x80000cf8
  19. #define MPC106_REG_DATA 0x80000cfc
  20. #define MPC106_ISA_IO_PHYS 0x80000000
  21. #define MPC106_ISA_IO_BUS 0x00000000
  22. #define MPC106_ISA_IO_SIZE 0x00800000
  23. #define MPC106_PCI_IO_PHYS 0x81000000
  24. #define MPC106_PCI_IO_BUS 0x01000000
  25. #define MPC106_PCI_IO_SIZE 0x3e800000
  26. #define MPC106_PCI_MEM_PHYS 0xc0000000
  27. #define MPC106_PCI_MEM_BUS 0x00000000
  28. #define MPC106_PCI_MEM_SIZE 0x3f000000
  29. #define MPC106_PCI_MEMORY_PHYS 0x00000000
  30. #define MPC106_PCI_MEMORY_BUS 0x80000000
  31. #define MPC106_PCI_MEMORY_SIZE 0x80000000
  32. #else
  33. #define MPC106_REG_ADDR 0xfec00cf8
  34. #define MPC106_REG_DATA 0xfee00cfc
  35. #define MPC106_ISA_MEM_PHYS 0xfd000000
  36. #define MPC106_ISA_MEM_BUS 0x00000000
  37. #define MPC106_ISA_MEM_SIZE 0x01000000
  38. #define MPC106_ISA_IO_PHYS 0xfe000000
  39. #define MPC106_ISA_IO_BUS 0x00000000
  40. #define MPC106_ISA_IO_SIZE 0x00800000
  41. #define MPC106_PCI_IO_PHYS 0xfe800000
  42. #define MPC106_PCI_IO_BUS 0x00800000
  43. #define MPC106_PCI_IO_SIZE 0x00400000
  44. #define MPC106_PCI_MEM_PHYS 0x80000000
  45. #define MPC106_PCI_MEM_BUS 0x80000000
  46. #define MPC106_PCI_MEM_SIZE 0x7d000000
  47. #define MPC106_PCI_MEMORY_PHYS 0x00000000
  48. #define MPC106_PCI_MEMORY_BUS 0x00000000
  49. #define MPC106_PCI_MEMORY_SIZE 0x40000000
  50. #endif
  51. #define CMD_SERR 0x0100
  52. #define PCI_CMD_MASTER 0x0004
  53. #define PCI_CMD_MEMEN 0x0002
  54. #define PCI_CMD_IOEN 0x0001
  55. #define PCI_STAT_NO_RSV_BITS 0xffff
  56. #define PCI_BUSNUM 0x40
  57. #define PCI_SUBBUSNUM 0x41
  58. #define PCI_DISCOUNT 0x42
  59. #define PCI_PICR1 0xA8
  60. #define PICR1_CF_CBA(value) ((value & 0xff) << 24)
  61. #define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22)
  62. #define PICR1_PROC_TYPE_603 0x40000
  63. #define PICR1_PROC_TYPE_604 0x60000
  64. #define PICR1_MCP_EN 0x800
  65. #define PICR1_CF_DPARK 0x200
  66. #define PICR1_CF_LOOP_SNOOP 0x10
  67. #define PICR1_CF_L2_COPY_BACK 0x2
  68. #define PICR1_CF_L2_CACHE_MASK 0x3
  69. #define PICR1_CF_APARK 0x8
  70. #define PICR1_ADDRESS_MAP 0x10000
  71. #define PICR1_XIO_MODE 0x80000
  72. #define PICR1_CF_CACHE_1G 0x200000
  73. #define PCI_PICR2 0xAC
  74. #define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18)
  75. #define PICR2_CF_FLUSH_L2 0x10000000
  76. #define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9)
  77. #define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2)
  78. #define PICR2_CF_INV_MODE 0x00001000
  79. #define PICR2_CF_MOD_HIGH 0x00020000
  80. #define PICR2_CF_HIT_HIGH 0x00010000
  81. #define PICR2_L2_SIZE_256K 0x00000000
  82. #define PICR2_L2_SIZE_512K 0x00000010
  83. #define PICR2_L2_SIZE_1MB 0x00000020
  84. #define PICR2_L2_EN 0x40000000
  85. #define PICR2_L2_UPDATE_EN 0x80000000
  86. #define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000
  87. #define PICR2_CF_FAST_CASTOUT 0x00000080
  88. #define PICR2_CF_WDATA 0x00000001
  89. #define PICR2_CF_DATA_RAM_PBURST 0x00400000
  90. /*
  91. * Memory controller
  92. */
  93. #define MPC106_MCCR1 0xF0
  94. #define MCCR1_TYPE_EDO 0x00020000
  95. #define MCCR1_BK0_9BITS 0x0
  96. #define MCCR1_BK0_10BITS 0x1
  97. #define MCCR1_BK0_11BITS 0x2
  98. #define MCCR1_BK0_12BITS 0x3
  99. #define MCCR1_BK1_9BITS 0x0
  100. #define MCCR1_BK1_10BITS 0x4
  101. #define MCCR1_BK1_11BITS 0x8
  102. #define MCCR1_BK1_12BITS 0xC
  103. #define MCCR1_BK2_9BITS 0x00
  104. #define MCCR1_BK2_10BITS 0x10
  105. #define MCCR1_BK2_11BITS 0x20
  106. #define MCCR1_BK2_12BITS 0x30
  107. #define MCCR1_BK3_9BITS 0x00
  108. #define MCCR1_BK3_10BITS 0x40
  109. #define MCCR1_BK3_11BITS 0x80
  110. #define MCCR1_BK3_12BITS 0xC0
  111. #define MCCR1_MEMGO 0x00080000
  112. #define MPC106_MCCR2 0xF4
  113. #define MPC106_MCCR3 0xF8
  114. #define MPC106_MCCR4 0xFC
  115. #define MPC106_MSAR1 0x80
  116. #define MPC106_EMSAR1 0x88
  117. #define MPC106_EMSAR2 0x8C
  118. #define MPC106_MEAR1 0x90
  119. #define MPC106_EMEAR1 0x98
  120. #define MPC106_EMEAR2 0x9C
  121. #define MPC106_MBER 0xA0
  122. #define MBER_BANK0 0x1
  123. #define MBER_BANK1 0x2
  124. #define MBER_BANK2 0x4
  125. #define MBER_BANK3 0x8
  126. #endif