mmc.h 29 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based (loosely) on the Linux code
  7. */
  8. #ifndef _MMC_H_
  9. #define _MMC_H_
  10. #include <linux/bitops.h>
  11. #include <linux/list.h>
  12. #include <linux/sizes.h>
  13. #include <linux/compiler.h>
  14. #include <linux/dma-direction.h>
  15. #include <part.h>
  16. struct bd_info;
  17. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  18. #define MMC_SUPPORTS_TUNING
  19. #endif
  20. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  21. #define MMC_SUPPORTS_TUNING
  22. #endif
  23. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  24. #define SD_VERSION_SD (1U << 31)
  25. #define MMC_VERSION_MMC (1U << 30)
  26. #define MAKE_SDMMC_VERSION(a, b, c) \
  27. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  28. #define MAKE_SD_VERSION(a, b, c) \
  29. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  30. #define MAKE_MMC_VERSION(a, b, c) \
  31. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  32. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  33. (((u32)(x) >> 16) & 0xff)
  34. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  35. (((u32)(x) >> 8) & 0xff)
  36. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  37. ((u32)(x) & 0xff)
  38. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  39. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  40. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  41. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  42. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  43. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  44. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  45. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  46. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  47. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  48. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  49. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  50. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  51. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  52. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  53. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  54. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  55. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  56. #define MMC_CAP(mode) (1 << mode)
  57. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  58. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  59. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  60. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  61. #define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
  62. #define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
  63. #define MMC_CAP_NONREMOVABLE BIT(14)
  64. #define MMC_CAP_NEEDS_POLL BIT(15)
  65. #define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
  66. #define MMC_MODE_8BIT BIT(30)
  67. #define MMC_MODE_4BIT BIT(29)
  68. #define MMC_MODE_1BIT BIT(28)
  69. #define MMC_MODE_SPI BIT(27)
  70. #define SD_DATA_4BIT 0x00040000
  71. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  72. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  73. #define MMC_DATA_READ 1
  74. #define MMC_DATA_WRITE 2
  75. #define MMC_CMD_GO_IDLE_STATE 0
  76. #define MMC_CMD_SEND_OP_COND 1
  77. #define MMC_CMD_ALL_SEND_CID 2
  78. #define MMC_CMD_SET_RELATIVE_ADDR 3
  79. #define MMC_CMD_SET_DSR 4
  80. #define MMC_CMD_SWITCH 6
  81. #define MMC_CMD_SELECT_CARD 7
  82. #define MMC_CMD_SEND_EXT_CSD 8
  83. #define MMC_CMD_SEND_CSD 9
  84. #define MMC_CMD_SEND_CID 10
  85. #define MMC_CMD_STOP_TRANSMISSION 12
  86. #define MMC_CMD_SEND_STATUS 13
  87. #define MMC_CMD_SET_BLOCKLEN 16
  88. #define MMC_CMD_READ_SINGLE_BLOCK 17
  89. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  90. #define MMC_CMD_SEND_TUNING_BLOCK 19
  91. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  92. #define MMC_CMD_SET_BLOCK_COUNT 23
  93. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  94. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  95. #define MMC_CMD_ERASE_GROUP_START 35
  96. #define MMC_CMD_ERASE_GROUP_END 36
  97. #define MMC_CMD_ERASE 38
  98. #define MMC_CMD_APP_CMD 55
  99. #define MMC_CMD_SPI_READ_OCR 58
  100. #define MMC_CMD_SPI_CRC_ON_OFF 59
  101. #define MMC_CMD_RES_MAN 62
  102. #define MMC_CMD62_ARG1 0xefac62ec
  103. #define MMC_CMD62_ARG2 0xcbaea7
  104. #define SD_CMD_SEND_RELATIVE_ADDR 3
  105. #define SD_CMD_SWITCH_FUNC 6
  106. #define SD_CMD_SEND_IF_COND 8
  107. #define SD_CMD_SWITCH_UHS18V 11
  108. #define SD_CMD_APP_SET_BUS_WIDTH 6
  109. #define SD_CMD_APP_SD_STATUS 13
  110. #define SD_CMD_ERASE_WR_BLK_START 32
  111. #define SD_CMD_ERASE_WR_BLK_END 33
  112. #define SD_CMD_APP_SEND_OP_COND 41
  113. #define SD_CMD_APP_SEND_SCR 51
  114. static inline bool mmc_is_tuning_cmd(uint cmdidx)
  115. {
  116. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  117. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  118. return true;
  119. return false;
  120. }
  121. /* SCR definitions in different words */
  122. #define SD_HIGHSPEED_BUSY 0x00020000
  123. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  124. #define UHS_SDR12_BUS_SPEED 0
  125. #define HIGH_SPEED_BUS_SPEED 1
  126. #define UHS_SDR25_BUS_SPEED 1
  127. #define UHS_SDR50_BUS_SPEED 2
  128. #define UHS_SDR104_BUS_SPEED 3
  129. #define UHS_DDR50_BUS_SPEED 4
  130. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  131. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  132. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  133. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  134. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  135. #define OCR_BUSY 0x80000000
  136. #define OCR_HCS 0x40000000
  137. #define OCR_S18R 0x1000000
  138. #define OCR_VOLTAGE_MASK 0x007FFF80
  139. #define OCR_ACCESS_MODE 0x60000000
  140. #define MMC_ERASE_ARG 0x00000000
  141. #define MMC_SECURE_ERASE_ARG 0x80000000
  142. #define MMC_TRIM_ARG 0x00000001
  143. #define MMC_DISCARD_ARG 0x00000003
  144. #define MMC_SECURE_TRIM1_ARG 0x80000001
  145. #define MMC_SECURE_TRIM2_ARG 0x80008000
  146. #define MMC_STATUS_MASK (~0x0206BF7F)
  147. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  148. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  149. #define MMC_STATUS_CURR_STATE (0xf << 9)
  150. #define MMC_STATUS_ERROR (1 << 19)
  151. #define MMC_STATE_PRG (7 << 9)
  152. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  153. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  154. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  155. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  156. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  157. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  158. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  159. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  160. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  161. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  162. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  163. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  164. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  165. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  166. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  167. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  168. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  169. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  170. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  171. addressed by index which are
  172. 1 in value field */
  173. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  174. addressed by index, which are
  175. 1 in value field */
  176. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  177. #define SD_SWITCH_CHECK 0
  178. #define SD_SWITCH_SWITCH 1
  179. /*
  180. * EXT_CSD fields
  181. */
  182. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  183. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  184. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  185. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  186. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  187. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  188. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  189. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  190. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  191. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  192. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  193. #define EXT_CSD_RPMB_MULT 168 /* RO */
  194. #define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
  195. #define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
  196. #define EXT_CSD_BOOT_WP_STATUS 174 /* R */
  197. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  198. #define EXT_CSD_BOOT_BUS_WIDTH 177
  199. #define EXT_CSD_PART_CONF 179 /* R/W */
  200. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  201. #define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
  202. #define EXT_CSD_HS_TIMING 185 /* R/W */
  203. #define EXT_CSD_REV 192 /* RO */
  204. #define EXT_CSD_CARD_TYPE 196 /* RO */
  205. #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
  206. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  207. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  208. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  209. #define EXT_CSD_BOOT_MULT 226 /* RO */
  210. #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
  211. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  212. /*
  213. * EXT_CSD field definitions
  214. */
  215. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  216. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  217. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  218. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  219. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  220. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  221. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  222. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  223. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  224. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  225. /* SDR mode @1.8V I/O */
  226. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  227. /* SDR mode @1.2V I/O */
  228. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  229. EXT_CSD_CARD_TYPE_HS200_1_2V)
  230. #define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
  231. #define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
  232. #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
  233. EXT_CSD_CARD_TYPE_HS400_1_2V)
  234. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  235. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  236. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  237. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  238. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  239. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  240. #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
  241. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  242. #define EXT_CSD_TIMING_HS 1 /* HS */
  243. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  244. #define EXT_CSD_TIMING_HS400 3 /* HS400 */
  245. #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
  246. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  247. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  248. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  249. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  250. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  251. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  252. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  253. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  254. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  255. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  256. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  257. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  258. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  259. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  260. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  261. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  262. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  263. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  264. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  265. #define R1_ILLEGAL_COMMAND (1 << 22)
  266. #define R1_APP_CMD (1 << 5)
  267. #define MMC_RSP_PRESENT (1 << 0)
  268. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  269. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  270. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  271. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  272. #define MMC_RSP_NONE (0)
  273. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  274. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  275. MMC_RSP_BUSY)
  276. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  277. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  278. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  279. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  280. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  281. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  282. #define MMCPART_NOAVAILABLE (0xff)
  283. #define PART_ACCESS_MASK (0x7)
  284. #define PART_SUPPORT (0x1)
  285. #define ENHNCD_SUPPORT (0x2)
  286. #define PART_ENH_ATTRIB (0x1f)
  287. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  288. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  289. #define MMC_QUIRK_RETRY_APP_CMD BIT(2)
  290. enum mmc_voltage {
  291. MMC_SIGNAL_VOLTAGE_000 = 0,
  292. MMC_SIGNAL_VOLTAGE_120 = 1,
  293. MMC_SIGNAL_VOLTAGE_180 = 2,
  294. MMC_SIGNAL_VOLTAGE_330 = 4,
  295. };
  296. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  297. MMC_SIGNAL_VOLTAGE_180 |\
  298. MMC_SIGNAL_VOLTAGE_330)
  299. /* Maximum block size for MMC */
  300. #define MMC_MAX_BLOCK_LEN 512
  301. /* The number of MMC physical partitions. These consist of:
  302. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  303. */
  304. #define MMC_NUM_BOOT_PARTITION 2
  305. #define MMC_PART_RPMB 3 /* RPMB partition number */
  306. /* timing specification used */
  307. #define MMC_TIMING_LEGACY 0
  308. #define MMC_TIMING_MMC_HS 1
  309. #define MMC_TIMING_SD_HS 2
  310. #define MMC_TIMING_UHS_SDR12 3
  311. #define MMC_TIMING_UHS_SDR25 4
  312. #define MMC_TIMING_UHS_SDR50 5
  313. #define MMC_TIMING_UHS_SDR104 6
  314. #define MMC_TIMING_UHS_DDR50 7
  315. #define MMC_TIMING_MMC_DDR52 8
  316. #define MMC_TIMING_MMC_HS200 9
  317. #define MMC_TIMING_MMC_HS400 10
  318. /* Driver model support */
  319. /**
  320. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  321. */
  322. struct mmc_uclass_priv {
  323. struct mmc *mmc;
  324. };
  325. /**
  326. * mmc_get_mmc_dev() - get the MMC struct pointer for a device
  327. *
  328. * Provided that the device is already probed and ready for use, this value
  329. * will be available.
  330. *
  331. * @dev: Device
  332. * @return associated mmc struct pointer if available, else NULL
  333. */
  334. struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
  335. /* End of driver model support */
  336. struct mmc_cid {
  337. unsigned long psn;
  338. unsigned short oid;
  339. unsigned char mid;
  340. unsigned char prv;
  341. unsigned char mdt;
  342. char pnm[7];
  343. };
  344. struct mmc_cmd {
  345. ushort cmdidx;
  346. uint resp_type;
  347. uint cmdarg;
  348. uint response[4];
  349. };
  350. struct mmc_data {
  351. union {
  352. char *dest;
  353. const char *src; /* src buffers don't get written to */
  354. };
  355. uint flags;
  356. uint blocks;
  357. uint blocksize;
  358. };
  359. /* forward decl. */
  360. struct mmc;
  361. #if CONFIG_IS_ENABLED(DM_MMC)
  362. struct dm_mmc_ops {
  363. /**
  364. * deferred_probe() - Some configurations that need to be deferred
  365. * to just before enumerating the device
  366. *
  367. * @dev: Device to init
  368. * @return 0 if Ok, -ve if error
  369. */
  370. int (*deferred_probe)(struct udevice *dev);
  371. /**
  372. * reinit() - Re-initialization to clear old configuration for
  373. * mmc rescan.
  374. *
  375. * @dev: Device to reinit
  376. * @return 0 if Ok, -ve if error
  377. */
  378. int (*reinit)(struct udevice *dev);
  379. /**
  380. * send_cmd() - Send a command to the MMC device
  381. *
  382. * @dev: Device to receive the command
  383. * @cmd: Command to send
  384. * @data: Additional data to send/receive
  385. * @return 0 if OK, -ve on error
  386. */
  387. int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
  388. struct mmc_data *data);
  389. /**
  390. * set_ios() - Set the I/O speed/width for an MMC device
  391. *
  392. * @dev: Device to update
  393. * @return 0 if OK, -ve on error
  394. */
  395. int (*set_ios)(struct udevice *dev);
  396. /**
  397. * get_cd() - See whether a card is present
  398. *
  399. * @dev: Device to check
  400. * @return 0 if not present, 1 if present, -ve on error
  401. */
  402. int (*get_cd)(struct udevice *dev);
  403. /**
  404. * get_wp() - See whether a card has write-protect enabled
  405. *
  406. * @dev: Device to check
  407. * @return 0 if write-enabled, 1 if write-protected, -ve on error
  408. */
  409. int (*get_wp)(struct udevice *dev);
  410. #ifdef MMC_SUPPORTS_TUNING
  411. /**
  412. * execute_tuning() - Start the tuning process
  413. *
  414. * @dev: Device to start the tuning
  415. * @opcode: Command opcode to send
  416. * @return 0 if OK, -ve on error
  417. */
  418. int (*execute_tuning)(struct udevice *dev, uint opcode);
  419. #endif
  420. /**
  421. * wait_dat0() - wait until dat0 is in the target state
  422. * (CLK must be running during the wait)
  423. *
  424. * @dev: Device to check
  425. * @state: target state
  426. * @timeout_us: timeout in us
  427. * @return 0 if dat0 is in the target state, -ve on error
  428. */
  429. int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
  430. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  431. /* set_enhanced_strobe() - set HS400 enhanced strobe */
  432. int (*set_enhanced_strobe)(struct udevice *dev);
  433. #endif
  434. /**
  435. * host_power_cycle - host specific tasks in power cycle sequence
  436. * Called between mmc_power_off() and
  437. * mmc_power_on()
  438. *
  439. * @dev: Device to check
  440. * @return 0 if not present, 1 if present, -ve on error
  441. */
  442. int (*host_power_cycle)(struct udevice *dev);
  443. /**
  444. * get_b_max - get maximum length of single transfer
  445. * Called before reading blocks from the card,
  446. * useful for system which have e.g. DMA limits
  447. * on various memory ranges.
  448. *
  449. * @dev: Device to check
  450. * @dst: Destination buffer in memory
  451. * @blkcnt: Total number of blocks in this transfer
  452. * @return maximum number of blocks for this transfer
  453. */
  454. int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
  455. /**
  456. * hs400_prepare_ddr - prepare to switch to DDR mode
  457. *
  458. * @dev: Device to check
  459. * @return 0 if success, -ve on error
  460. */
  461. int (*hs400_prepare_ddr)(struct udevice *dev);
  462. };
  463. #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
  464. int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  465. struct mmc_data *data);
  466. int dm_mmc_set_ios(struct udevice *dev);
  467. int dm_mmc_get_cd(struct udevice *dev);
  468. int dm_mmc_get_wp(struct udevice *dev);
  469. int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
  470. int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout_us);
  471. int dm_mmc_host_power_cycle(struct udevice *dev);
  472. int dm_mmc_deferred_probe(struct udevice *dev);
  473. int dm_mmc_reinit(struct udevice *dev);
  474. int dm_mmc_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt);
  475. /* Transition functions for compatibility */
  476. int mmc_set_ios(struct mmc *mmc);
  477. int mmc_getcd(struct mmc *mmc);
  478. int mmc_getwp(struct mmc *mmc);
  479. int mmc_execute_tuning(struct mmc *mmc, uint opcode);
  480. int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
  481. int mmc_set_enhanced_strobe(struct mmc *mmc);
  482. int mmc_host_power_cycle(struct mmc *mmc);
  483. int mmc_deferred_probe(struct mmc *mmc);
  484. int mmc_reinit(struct mmc *mmc);
  485. int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
  486. int mmc_hs400_prepare_ddr(struct mmc *mmc);
  487. #else
  488. struct mmc_ops {
  489. int (*send_cmd)(struct mmc *mmc,
  490. struct mmc_cmd *cmd, struct mmc_data *data);
  491. int (*set_ios)(struct mmc *mmc);
  492. int (*init)(struct mmc *mmc);
  493. int (*getcd)(struct mmc *mmc);
  494. int (*getwp)(struct mmc *mmc);
  495. int (*host_power_cycle)(struct mmc *mmc);
  496. int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
  497. };
  498. static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
  499. {
  500. return 0;
  501. }
  502. #endif
  503. struct mmc_config {
  504. const char *name;
  505. #if !CONFIG_IS_ENABLED(DM_MMC)
  506. const struct mmc_ops *ops;
  507. #endif
  508. uint host_caps;
  509. uint voltages;
  510. uint f_min;
  511. uint f_max;
  512. uint b_max;
  513. unsigned char part_type;
  514. };
  515. struct sd_ssr {
  516. unsigned int au; /* In sectors */
  517. unsigned int erase_timeout; /* In milliseconds */
  518. unsigned int erase_offset; /* In milliseconds */
  519. };
  520. enum bus_mode {
  521. MMC_LEGACY,
  522. MMC_HS,
  523. SD_HS,
  524. MMC_HS_52,
  525. MMC_DDR_52,
  526. UHS_SDR12,
  527. UHS_SDR25,
  528. UHS_SDR50,
  529. UHS_DDR50,
  530. UHS_SDR104,
  531. MMC_HS_200,
  532. MMC_HS_400,
  533. MMC_HS_400_ES,
  534. MMC_MODES_END
  535. };
  536. const char *mmc_mode_name(enum bus_mode mode);
  537. void mmc_dump_capabilities(const char *text, uint caps);
  538. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  539. {
  540. if (mode == MMC_DDR_52)
  541. return true;
  542. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  543. else if (mode == UHS_DDR50)
  544. return true;
  545. #endif
  546. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  547. else if (mode == MMC_HS_400)
  548. return true;
  549. #endif
  550. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  551. else if (mode == MMC_HS_400_ES)
  552. return true;
  553. #endif
  554. else
  555. return false;
  556. }
  557. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  558. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  559. MMC_CAP(UHS_DDR50))
  560. static inline bool supports_uhs(uint caps)
  561. {
  562. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  563. return (caps & UHS_CAPS) ? true : false;
  564. #else
  565. return false;
  566. #endif
  567. }
  568. /*
  569. * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  570. * with mmc_get_mmc_dev().
  571. *
  572. * TODO struct mmc should be in mmc_private but it's hard to fix right now
  573. */
  574. struct mmc {
  575. #if !CONFIG_IS_ENABLED(BLK)
  576. struct list_head link;
  577. #endif
  578. const struct mmc_config *cfg; /* provided configuration */
  579. uint version;
  580. void *priv;
  581. uint has_init;
  582. int high_capacity;
  583. bool clk_disable; /* true if the clock can be turned off */
  584. uint bus_width;
  585. uint clock;
  586. uint saved_clock;
  587. enum mmc_voltage signal_voltage;
  588. uint card_caps;
  589. uint host_caps;
  590. uint ocr;
  591. uint dsr;
  592. uint dsr_imp;
  593. uint scr[2];
  594. uint csd[4];
  595. uint cid[4];
  596. ushort rca;
  597. u8 part_support;
  598. u8 part_attr;
  599. u8 wr_rel_set;
  600. u8 part_config;
  601. u8 gen_cmd6_time; /* units: 10 ms */
  602. u8 part_switch_time; /* units: 10 ms */
  603. uint tran_speed;
  604. uint legacy_speed; /* speed for the legacy mode provided by the card */
  605. uint read_bl_len;
  606. #if CONFIG_IS_ENABLED(MMC_WRITE)
  607. uint write_bl_len;
  608. uint erase_grp_size; /* in 512-byte sectors */
  609. #endif
  610. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  611. uint hc_wp_grp_size; /* in 512-byte sectors */
  612. #endif
  613. #if CONFIG_IS_ENABLED(MMC_WRITE)
  614. struct sd_ssr ssr; /* SD status register */
  615. #endif
  616. u64 capacity;
  617. u64 capacity_user;
  618. u64 capacity_boot;
  619. u64 capacity_rpmb;
  620. u64 capacity_gp[4];
  621. #ifndef CONFIG_SPL_BUILD
  622. u64 enh_user_start;
  623. u64 enh_user_size;
  624. #endif
  625. #if !CONFIG_IS_ENABLED(BLK)
  626. struct blk_desc block_dev;
  627. #endif
  628. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  629. char init_in_progress; /* 1 if we have done mmc_start_init() */
  630. char preinit; /* start init as early as possible */
  631. int ddr_mode;
  632. #if CONFIG_IS_ENABLED(DM_MMC)
  633. struct udevice *dev; /* Device for this MMC controller */
  634. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  635. struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
  636. struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
  637. #endif
  638. #endif
  639. u8 *ext_csd;
  640. u32 cardtype; /* cardtype read from the MMC */
  641. enum mmc_voltage current_voltage;
  642. enum bus_mode selected_mode; /* mode currently used */
  643. enum bus_mode best_mode; /* best mode is the supported mode with the
  644. * highest bandwidth. It may not always be the
  645. * operating mode due to limitations when
  646. * accessing the boot partitions
  647. */
  648. u32 quirks;
  649. u8 hs400_tuning;
  650. };
  651. struct mmc_hwpart_conf {
  652. struct {
  653. uint enh_start; /* in 512-byte sectors */
  654. uint enh_size; /* in 512-byte sectors, if 0 no enh area */
  655. unsigned wr_rel_change : 1;
  656. unsigned wr_rel_set : 1;
  657. } user;
  658. struct {
  659. uint size; /* in 512-byte sectors */
  660. unsigned enhanced : 1;
  661. unsigned wr_rel_change : 1;
  662. unsigned wr_rel_set : 1;
  663. } gp_part[4];
  664. };
  665. enum mmc_hwpart_conf_mode {
  666. MMC_HWPART_CONF_CHECK,
  667. MMC_HWPART_CONF_SET,
  668. MMC_HWPART_CONF_COMPLETE,
  669. };
  670. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
  671. /**
  672. * mmc_bind() - Set up a new MMC device ready for probing
  673. *
  674. * A child block device is bound with the IF_TYPE_MMC interface type. This
  675. * allows the device to be used with CONFIG_BLK
  676. *
  677. * @dev: MMC device to set up
  678. * @mmc: MMC struct
  679. * @cfg: MMC configuration
  680. * @return 0 if OK, -ve on error
  681. */
  682. int mmc_bind(struct udevice *dev, struct mmc *mmc,
  683. const struct mmc_config *cfg);
  684. void mmc_destroy(struct mmc *mmc);
  685. /**
  686. * mmc_unbind() - Unbind a MMC device's child block device
  687. *
  688. * @dev: MMC device
  689. * @return 0 if OK, -ve on error
  690. */
  691. int mmc_unbind(struct udevice *dev);
  692. int mmc_initialize(struct bd_info *bis);
  693. int mmc_init_device(int num);
  694. int mmc_init(struct mmc *mmc);
  695. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
  696. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  697. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  698. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  699. int mmc_deinit(struct mmc *mmc);
  700. #endif
  701. /**
  702. * mmc_of_parse() - Parse the device tree to get the capabilities of the host
  703. *
  704. * @dev: MMC device
  705. * @cfg: MMC configuration
  706. * @return 0 if OK, -ve on error
  707. */
  708. int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
  709. int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
  710. /**
  711. * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
  712. *
  713. * @voltage: The mmc_voltage to convert
  714. * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
  715. */
  716. int mmc_voltage_to_mv(enum mmc_voltage voltage);
  717. /**
  718. * mmc_set_clock() - change the bus clock
  719. * @mmc: MMC struct
  720. * @clock: bus frequency in Hz
  721. * @disable: flag indicating if the clock must on or off
  722. * @return 0 if OK, -ve on error
  723. */
  724. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
  725. #define MMC_CLK_ENABLE false
  726. #define MMC_CLK_DISABLE true
  727. struct mmc *find_mmc_device(int dev_num);
  728. int mmc_set_dev(int dev_num);
  729. void print_mmc_devices(char separator);
  730. /**
  731. * get_mmc_num() - get the total MMC device number
  732. *
  733. * @return 0 if there is no MMC device, else the number of devices
  734. */
  735. int get_mmc_num(void);
  736. int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
  737. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  738. enum mmc_hwpart_conf_mode mode);
  739. #if !CONFIG_IS_ENABLED(DM_MMC)
  740. int mmc_getcd(struct mmc *mmc);
  741. int board_mmc_getcd(struct mmc *mmc);
  742. int mmc_getwp(struct mmc *mmc);
  743. int board_mmc_getwp(struct mmc *mmc);
  744. #endif
  745. int mmc_set_dsr(struct mmc *mmc, u16 val);
  746. /* Function to change the size of boot partition and rpmb partitions */
  747. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  748. unsigned long rpmbsize);
  749. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  750. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  751. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  752. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  753. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  754. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  755. /* Functions to read / write the RPMB partition */
  756. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  757. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  758. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  759. unsigned short cnt, unsigned char *key);
  760. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  761. unsigned short cnt, unsigned char *key);
  762. /**
  763. * mmc_rpmb_route_frames() - route RPMB data frames
  764. * @mmc Pointer to a MMC device struct
  765. * @req Request data frames
  766. * @reqlen Length of data frames in bytes
  767. * @rsp Supplied buffer for response data frames
  768. * @rsplen Length of supplied buffer for response data frames
  769. *
  770. * The RPMB data frames are routed to/from some external entity, for
  771. * example a Trusted Exectuion Environment in an arm TrustZone protected
  772. * secure world. It's expected that it's the external entity who is in
  773. * control of the RPMB key.
  774. *
  775. * Returns 0 on success, < 0 on error.
  776. */
  777. int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
  778. void *rsp, unsigned long rsplen);
  779. #ifdef CONFIG_CMD_BKOPS_ENABLE
  780. int mmc_set_bkops_enable(struct mmc *mmc);
  781. #endif
  782. /**
  783. * Start device initialization and return immediately; it does not block on
  784. * polling OCR (operation condition register) status. Useful for checking
  785. * the presence of SD/eMMC when no card detect logic is available.
  786. *
  787. * @param mmc Pointer to a MMC device struct
  788. * @return 0 on success, <0 on error.
  789. */
  790. int mmc_get_op_cond(struct mmc *mmc);
  791. /**
  792. * Start device initialization and return immediately; it does not block on
  793. * polling OCR (operation condition register) status. Then you should call
  794. * mmc_init, which would block on polling OCR status and complete the device
  795. * initializatin.
  796. *
  797. * @param mmc Pointer to a MMC device struct
  798. * @return 0 on success, <0 on error.
  799. */
  800. int mmc_start_init(struct mmc *mmc);
  801. /**
  802. * Set preinit flag of mmc device.
  803. *
  804. * This will cause the device to be pre-inited during mmc_initialize(),
  805. * which may save boot time if the device is not accessed until later.
  806. * Some eMMC devices take 200-300ms to init, but unfortunately they
  807. * must be sent a series of commands to even get them to start preparing
  808. * for operation.
  809. *
  810. * @param mmc Pointer to a MMC device struct
  811. * @param preinit preinit flag value
  812. */
  813. void mmc_set_preinit(struct mmc *mmc, int preinit);
  814. #ifdef CONFIG_MMC_SPI
  815. #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
  816. #else
  817. #define mmc_host_is_spi(mmc) 0
  818. #endif
  819. #define mmc_dev(x) ((x)->dev)
  820. void board_mmc_power_init(void);
  821. int board_mmc_init(struct bd_info *bis);
  822. int cpu_mmc_init(struct bd_info *bis);
  823. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  824. # ifdef CONFIG_SYS_MMC_ENV_PART
  825. extern uint mmc_get_env_part(struct mmc *mmc);
  826. # endif
  827. int mmc_get_env_dev(void);
  828. /* Minimum partition switch timeout in units of 10-milliseconds */
  829. #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
  830. /* Set block count limit because of 16 bit register limit on some hardware*/
  831. #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
  832. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
  833. #endif
  834. /**
  835. * mmc_get_blk_desc() - Get the block descriptor for an MMC device
  836. *
  837. * @mmc: MMC device
  838. * @return block device if found, else NULL
  839. */
  840. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
  841. /**
  842. * mmc_send_ext_csd() - read the extended CSD register
  843. *
  844. * @mmc: MMC device
  845. * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
  846. * the caller, e.g. using
  847. * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
  848. * Return: 0 for success
  849. */
  850. int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
  851. /**
  852. * mmc_boot_wp() - power on write protect boot partitions
  853. *
  854. * The boot partitions are write protected until the next power cycle.
  855. *
  856. * Return: 0 for success
  857. */
  858. int mmc_boot_wp(struct mmc *mmc);
  859. static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
  860. {
  861. return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  862. }
  863. #endif /* _MMC_H_ */