rawnand.h 42 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
  4. * Steven J. Hill <sjhill@realitydiluted.com>
  5. * Thomas Gleixner <tglx@linutronix.de>
  6. *
  7. * Info:
  8. * Contains standard defines and IDs for NAND flash devices
  9. *
  10. * Changelog:
  11. * See git changelog.
  12. */
  13. #ifndef __LINUX_MTD_RAWNAND_H
  14. #define __LINUX_MTD_RAWNAND_H
  15. #include <config.h>
  16. #include <dm/device.h>
  17. #include <linux/bitops.h>
  18. #include <linux/compat.h>
  19. #include <linux/mtd/mtd.h>
  20. #include <linux/mtd/flashchip.h>
  21. #include <linux/mtd/bbm.h>
  22. #include <asm/cache.h>
  23. struct mtd_info;
  24. struct nand_chip;
  25. struct nand_flash_dev;
  26. struct device_node;
  27. /* Get the flash and manufacturer id and lookup if the type is supported. */
  28. struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
  29. struct nand_chip *chip,
  30. int *maf_id, int *dev_id,
  31. struct nand_flash_dev *type);
  32. /* Scan and identify a NAND device */
  33. int nand_scan(struct mtd_info *mtd, int max_chips);
  34. /*
  35. * Separate phases of nand_scan(), allowing board driver to intervene
  36. * and override command or ECC setup according to flash type.
  37. */
  38. int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  39. struct nand_flash_dev *table);
  40. int nand_scan_tail(struct mtd_info *mtd);
  41. /* Free resources held by the NAND device */
  42. void nand_release(struct mtd_info *mtd);
  43. /* Internal helper for board drivers which need to override command function */
  44. void nand_wait_ready(struct mtd_info *mtd);
  45. /*
  46. * This constant declares the max. oobsize / page, which
  47. * is supported now. If you add a chip with bigger oobsize/page
  48. * adjust this accordingly.
  49. */
  50. #define NAND_MAX_OOBSIZE 1664
  51. #define NAND_MAX_PAGESIZE 16384
  52. /*
  53. * Constants for hardware specific CLE/ALE/NCE function
  54. *
  55. * These are bits which can be or'ed to set/clear multiple
  56. * bits in one go.
  57. */
  58. /* Select the chip by setting nCE to low */
  59. #define NAND_NCE 0x01
  60. /* Select the command latch by setting CLE to high */
  61. #define NAND_CLE 0x02
  62. /* Select the address latch by setting ALE to high */
  63. #define NAND_ALE 0x04
  64. #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
  65. #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
  66. #define NAND_CTRL_CHANGE 0x80
  67. /*
  68. * Standard NAND flash commands
  69. */
  70. #define NAND_CMD_READ0 0
  71. #define NAND_CMD_READ1 1
  72. #define NAND_CMD_RNDOUT 5
  73. #define NAND_CMD_PAGEPROG 0x10
  74. #define NAND_CMD_READOOB 0x50
  75. #define NAND_CMD_ERASE1 0x60
  76. #define NAND_CMD_STATUS 0x70
  77. #define NAND_CMD_SEQIN 0x80
  78. #define NAND_CMD_RNDIN 0x85
  79. #define NAND_CMD_READID 0x90
  80. #define NAND_CMD_ERASE2 0xd0
  81. #define NAND_CMD_PARAM 0xec
  82. #define NAND_CMD_GET_FEATURES 0xee
  83. #define NAND_CMD_SET_FEATURES 0xef
  84. #define NAND_CMD_RESET 0xff
  85. #define NAND_CMD_LOCK 0x2a
  86. #define NAND_CMD_UNLOCK1 0x23
  87. #define NAND_CMD_UNLOCK2 0x24
  88. /* Extended commands for large page devices */
  89. #define NAND_CMD_READSTART 0x30
  90. #define NAND_CMD_RNDOUTSTART 0xE0
  91. #define NAND_CMD_CACHEDPROG 0x15
  92. /* Extended commands for AG-AND device */
  93. /*
  94. * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  95. * there is no way to distinguish that from NAND_CMD_READ0
  96. * until the remaining sequence of commands has been completed
  97. * so add a high order bit and mask it off in the command.
  98. */
  99. #define NAND_CMD_DEPLETE1 0x100
  100. #define NAND_CMD_DEPLETE2 0x38
  101. #define NAND_CMD_STATUS_MULTI 0x71
  102. #define NAND_CMD_STATUS_ERROR 0x72
  103. /* multi-bank error status (banks 0-3) */
  104. #define NAND_CMD_STATUS_ERROR0 0x73
  105. #define NAND_CMD_STATUS_ERROR1 0x74
  106. #define NAND_CMD_STATUS_ERROR2 0x75
  107. #define NAND_CMD_STATUS_ERROR3 0x76
  108. #define NAND_CMD_STATUS_RESET 0x7f
  109. #define NAND_CMD_STATUS_CLEAR 0xff
  110. #define NAND_CMD_NONE -1
  111. /* Status bits */
  112. #define NAND_STATUS_FAIL 0x01
  113. #define NAND_STATUS_FAIL_N1 0x02
  114. #define NAND_STATUS_TRUE_READY 0x20
  115. #define NAND_STATUS_READY 0x40
  116. #define NAND_STATUS_WP 0x80
  117. #define NAND_DATA_IFACE_CHECK_ONLY -1
  118. /*
  119. * Constants for ECC_MODES
  120. */
  121. typedef enum {
  122. NAND_ECC_NONE,
  123. NAND_ECC_SOFT,
  124. NAND_ECC_HW,
  125. NAND_ECC_HW_SYNDROME,
  126. NAND_ECC_HW_OOB_FIRST,
  127. NAND_ECC_SOFT_BCH,
  128. } nand_ecc_modes_t;
  129. enum nand_ecc_algo {
  130. NAND_ECC_UNKNOWN,
  131. NAND_ECC_HAMMING,
  132. NAND_ECC_BCH,
  133. };
  134. /*
  135. * Constants for Hardware ECC
  136. */
  137. /* Reset Hardware ECC for read */
  138. #define NAND_ECC_READ 0
  139. /* Reset Hardware ECC for write */
  140. #define NAND_ECC_WRITE 1
  141. /* Enable Hardware ECC before syndrome is read back from flash */
  142. #define NAND_ECC_READSYN 2
  143. /*
  144. * Enable generic NAND 'page erased' check. This check is only done when
  145. * ecc.correct() returns -EBADMSG.
  146. * Set this flag if your implementation does not fix bitflips in erased
  147. * pages and you want to rely on the default implementation.
  148. */
  149. #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
  150. #define NAND_ECC_MAXIMIZE BIT(1)
  151. /*
  152. * If your controller already sends the required NAND commands when
  153. * reading or writing a page, then the framework is not supposed to
  154. * send READ0 and SEQIN/PAGEPROG respectively.
  155. */
  156. #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
  157. /* Bit mask for flags passed to do_nand_read_ecc */
  158. #define NAND_GET_DEVICE 0x80
  159. /*
  160. * Option constants for bizarre disfunctionality and real
  161. * features.
  162. */
  163. /* Buswidth is 16 bit */
  164. #define NAND_BUSWIDTH_16 0x00000002
  165. /* Device supports partial programming without padding */
  166. #define NAND_NO_PADDING 0x00000004
  167. /* Chip has cache program function */
  168. #define NAND_CACHEPRG 0x00000008
  169. /* Chip has copy back function */
  170. #define NAND_COPYBACK 0x00000010
  171. /*
  172. * Chip requires ready check on read (for auto-incremented sequential read).
  173. * True only for small page devices; large page devices do not support
  174. * autoincrement.
  175. */
  176. #define NAND_NEED_READRDY 0x00000100
  177. /* Chip does not allow subpage writes */
  178. #define NAND_NO_SUBPAGE_WRITE 0x00000200
  179. /* Device is one of 'new' xD cards that expose fake nand command set */
  180. #define NAND_BROKEN_XD 0x00000400
  181. /* Device behaves just like nand, but is readonly */
  182. #define NAND_ROM 0x00000800
  183. /* Device supports subpage reads */
  184. #define NAND_SUBPAGE_READ 0x00001000
  185. /*
  186. * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
  187. * patterns.
  188. */
  189. #define NAND_NEED_SCRAMBLING 0x00002000
  190. /* Device needs 3rd row address cycle */
  191. #define NAND_ROW_ADDR_3 0x00004000
  192. /* Options valid for Samsung large page devices */
  193. #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
  194. /* Macros to identify the above */
  195. #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  196. #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
  197. #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
  198. /* Non chip related options */
  199. /* This option skips the bbt scan during initialization. */
  200. #define NAND_SKIP_BBTSCAN 0x00010000
  201. /*
  202. * This option is defined if the board driver allocates its own buffers
  203. * (e.g. because it needs them DMA-coherent).
  204. */
  205. #define NAND_OWN_BUFFERS 0x00020000
  206. /* Chip may not exist, so silence any errors in scan */
  207. #define NAND_SCAN_SILENT_NODEV 0x00040000
  208. /*
  209. * Autodetect nand buswidth with readid/onfi.
  210. * This suppose the driver will configure the hardware in 8 bits mode
  211. * when calling nand_scan_ident, and update its configuration
  212. * before calling nand_scan_tail.
  213. */
  214. #define NAND_BUSWIDTH_AUTO 0x00080000
  215. /*
  216. * This option could be defined by controller drivers to protect against
  217. * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
  218. */
  219. #define NAND_USE_BOUNCE_BUFFER 0x00100000
  220. /* Options set by nand scan */
  221. /* bbt has already been read */
  222. #define NAND_BBT_SCANNED 0x40000000
  223. /* Nand scan has allocated controller struct */
  224. #define NAND_CONTROLLER_ALLOC 0x80000000
  225. /* Cell info constants */
  226. #define NAND_CI_CHIPNR_MSK 0x03
  227. #define NAND_CI_CELLTYPE_MSK 0x0C
  228. #define NAND_CI_CELLTYPE_SHIFT 2
  229. /* ONFI features */
  230. #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
  231. #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
  232. /* ONFI timing mode, used in both asynchronous and synchronous mode */
  233. #define ONFI_TIMING_MODE_0 (1 << 0)
  234. #define ONFI_TIMING_MODE_1 (1 << 1)
  235. #define ONFI_TIMING_MODE_2 (1 << 2)
  236. #define ONFI_TIMING_MODE_3 (1 << 3)
  237. #define ONFI_TIMING_MODE_4 (1 << 4)
  238. #define ONFI_TIMING_MODE_5 (1 << 5)
  239. #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
  240. /* ONFI feature address */
  241. #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
  242. /* Vendor-specific feature address (Micron) */
  243. #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
  244. /* ONFI subfeature parameters length */
  245. #define ONFI_SUBFEATURE_PARAM_LEN 4
  246. /* ONFI optional commands SET/GET FEATURES supported? */
  247. #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
  248. struct nand_onfi_params {
  249. /* rev info and features block */
  250. /* 'O' 'N' 'F' 'I' */
  251. u8 sig[4];
  252. __le16 revision;
  253. __le16 features;
  254. __le16 opt_cmd;
  255. u8 reserved0[2];
  256. __le16 ext_param_page_length; /* since ONFI 2.1 */
  257. u8 num_of_param_pages; /* since ONFI 2.1 */
  258. u8 reserved1[17];
  259. /* manufacturer information block */
  260. char manufacturer[12];
  261. char model[20];
  262. u8 jedec_id;
  263. __le16 date_code;
  264. u8 reserved2[13];
  265. /* memory organization block */
  266. __le32 byte_per_page;
  267. __le16 spare_bytes_per_page;
  268. __le32 data_bytes_per_ppage;
  269. __le16 spare_bytes_per_ppage;
  270. __le32 pages_per_block;
  271. __le32 blocks_per_lun;
  272. u8 lun_count;
  273. u8 addr_cycles;
  274. u8 bits_per_cell;
  275. __le16 bb_per_lun;
  276. __le16 block_endurance;
  277. u8 guaranteed_good_blocks;
  278. __le16 guaranteed_block_endurance;
  279. u8 programs_per_page;
  280. u8 ppage_attr;
  281. u8 ecc_bits;
  282. u8 interleaved_bits;
  283. u8 interleaved_ops;
  284. u8 reserved3[13];
  285. /* electrical parameter block */
  286. u8 io_pin_capacitance_max;
  287. __le16 async_timing_mode;
  288. __le16 program_cache_timing_mode;
  289. __le16 t_prog;
  290. __le16 t_bers;
  291. __le16 t_r;
  292. __le16 t_ccs;
  293. __le16 src_sync_timing_mode;
  294. u8 src_ssync_features;
  295. __le16 clk_pin_capacitance_typ;
  296. __le16 io_pin_capacitance_typ;
  297. __le16 input_pin_capacitance_typ;
  298. u8 input_pin_capacitance_max;
  299. u8 driver_strength_support;
  300. __le16 t_int_r;
  301. __le16 t_adl;
  302. u8 reserved4[8];
  303. /* vendor */
  304. __le16 vendor_revision;
  305. u8 vendor[88];
  306. __le16 crc;
  307. } __packed;
  308. #define ONFI_CRC_BASE 0x4F4E
  309. /* Extended ECC information Block Definition (since ONFI 2.1) */
  310. struct onfi_ext_ecc_info {
  311. u8 ecc_bits;
  312. u8 codeword_size;
  313. __le16 bb_per_lun;
  314. __le16 block_endurance;
  315. u8 reserved[2];
  316. } __packed;
  317. #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
  318. #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
  319. #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
  320. struct onfi_ext_section {
  321. u8 type;
  322. u8 length;
  323. } __packed;
  324. #define ONFI_EXT_SECTION_MAX 8
  325. /* Extended Parameter Page Definition (since ONFI 2.1) */
  326. struct onfi_ext_param_page {
  327. __le16 crc;
  328. u8 sig[4]; /* 'E' 'P' 'P' 'S' */
  329. u8 reserved0[10];
  330. struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
  331. /*
  332. * The actual size of the Extended Parameter Page is in
  333. * @ext_param_page_length of nand_onfi_params{}.
  334. * The following are the variable length sections.
  335. * So we do not add any fields below. Please see the ONFI spec.
  336. */
  337. } __packed;
  338. struct nand_onfi_vendor_micron {
  339. u8 two_plane_read;
  340. u8 read_cache;
  341. u8 read_unique_id;
  342. u8 dq_imped;
  343. u8 dq_imped_num_settings;
  344. u8 dq_imped_feat_addr;
  345. u8 rb_pulldown_strength;
  346. u8 rb_pulldown_strength_feat_addr;
  347. u8 rb_pulldown_strength_num_settings;
  348. u8 otp_mode;
  349. u8 otp_page_start;
  350. u8 otp_data_prot_addr;
  351. u8 otp_num_pages;
  352. u8 otp_feat_addr;
  353. u8 read_retry_options;
  354. u8 reserved[72];
  355. u8 param_revision;
  356. } __packed;
  357. struct jedec_ecc_info {
  358. u8 ecc_bits;
  359. u8 codeword_size;
  360. __le16 bb_per_lun;
  361. __le16 block_endurance;
  362. u8 reserved[2];
  363. } __packed;
  364. /* JEDEC features */
  365. #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
  366. struct nand_jedec_params {
  367. /* rev info and features block */
  368. /* 'J' 'E' 'S' 'D' */
  369. u8 sig[4];
  370. __le16 revision;
  371. __le16 features;
  372. u8 opt_cmd[3];
  373. __le16 sec_cmd;
  374. u8 num_of_param_pages;
  375. u8 reserved0[18];
  376. /* manufacturer information block */
  377. char manufacturer[12];
  378. char model[20];
  379. u8 jedec_id[6];
  380. u8 reserved1[10];
  381. /* memory organization block */
  382. __le32 byte_per_page;
  383. __le16 spare_bytes_per_page;
  384. u8 reserved2[6];
  385. __le32 pages_per_block;
  386. __le32 blocks_per_lun;
  387. u8 lun_count;
  388. u8 addr_cycles;
  389. u8 bits_per_cell;
  390. u8 programs_per_page;
  391. u8 multi_plane_addr;
  392. u8 multi_plane_op_attr;
  393. u8 reserved3[38];
  394. /* electrical parameter block */
  395. __le16 async_sdr_speed_grade;
  396. __le16 toggle_ddr_speed_grade;
  397. __le16 sync_ddr_speed_grade;
  398. u8 async_sdr_features;
  399. u8 toggle_ddr_features;
  400. u8 sync_ddr_features;
  401. __le16 t_prog;
  402. __le16 t_bers;
  403. __le16 t_r;
  404. __le16 t_r_multi_plane;
  405. __le16 t_ccs;
  406. __le16 io_pin_capacitance_typ;
  407. __le16 input_pin_capacitance_typ;
  408. __le16 clk_pin_capacitance_typ;
  409. u8 driver_strength_support;
  410. __le16 t_adl;
  411. u8 reserved4[36];
  412. /* ECC and endurance block */
  413. u8 guaranteed_good_blocks;
  414. __le16 guaranteed_block_endurance;
  415. struct jedec_ecc_info ecc_info[4];
  416. u8 reserved5[29];
  417. /* reserved */
  418. u8 reserved6[148];
  419. /* vendor */
  420. __le16 vendor_rev_num;
  421. u8 reserved7[88];
  422. /* CRC for Parameter Page */
  423. __le16 crc;
  424. } __packed;
  425. /**
  426. * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  427. * @lock: protection lock
  428. * @active: the mtd device which holds the controller currently
  429. * @wq: wait queue to sleep on if a NAND operation is in
  430. * progress used instead of the per chip wait queue
  431. * when a hw controller is available.
  432. */
  433. struct nand_hw_control {
  434. spinlock_t lock;
  435. struct nand_chip *active;
  436. };
  437. static inline void nand_hw_control_init(struct nand_hw_control *nfc)
  438. {
  439. nfc->active = NULL;
  440. spin_lock_init(&nfc->lock);
  441. init_waitqueue_head(&nfc->wq);
  442. }
  443. /**
  444. * struct nand_ecc_step_info - ECC step information of ECC engine
  445. * @stepsize: data bytes per ECC step
  446. * @strengths: array of supported strengths
  447. * @nstrengths: number of supported strengths
  448. */
  449. struct nand_ecc_step_info {
  450. int stepsize;
  451. const int *strengths;
  452. int nstrengths;
  453. };
  454. /**
  455. * struct nand_ecc_caps - capability of ECC engine
  456. * @stepinfos: array of ECC step information
  457. * @nstepinfos: number of ECC step information
  458. * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
  459. */
  460. struct nand_ecc_caps {
  461. const struct nand_ecc_step_info *stepinfos;
  462. int nstepinfos;
  463. int (*calc_ecc_bytes)(int step_size, int strength);
  464. };
  465. /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
  466. #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
  467. static const int __name##_strengths[] = { __VA_ARGS__ }; \
  468. static const struct nand_ecc_step_info __name##_stepinfo = { \
  469. .stepsize = __step, \
  470. .strengths = __name##_strengths, \
  471. .nstrengths = ARRAY_SIZE(__name##_strengths), \
  472. }; \
  473. static const struct nand_ecc_caps __name = { \
  474. .stepinfos = &__name##_stepinfo, \
  475. .nstepinfos = 1, \
  476. .calc_ecc_bytes = __calc, \
  477. }
  478. /**
  479. * struct nand_ecc_ctrl - Control structure for ECC
  480. * @mode: ECC mode
  481. * @algo: ECC algorithm
  482. * @steps: number of ECC steps per page
  483. * @size: data bytes per ECC step
  484. * @bytes: ECC bytes per step
  485. * @strength: max number of correctible bits per ECC step
  486. * @total: total number of ECC bytes per page
  487. * @prepad: padding information for syndrome based ECC generators
  488. * @postpad: padding information for syndrome based ECC generators
  489. * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
  490. * @layout: ECC layout control struct pointer
  491. * @priv: pointer to private ECC control data
  492. * @hwctl: function to control hardware ECC generator. Must only
  493. * be provided if an hardware ECC is available
  494. * @calculate: function for ECC calculation or readback from ECC hardware
  495. * @correct: function for ECC correction, matching to ECC generator (sw/hw).
  496. * Should return a positive number representing the number of
  497. * corrected bitflips, -EBADMSG if the number of bitflips exceed
  498. * ECC strength, or any other error code if the error is not
  499. * directly related to correction.
  500. * If -EBADMSG is returned the input buffers should be left
  501. * untouched.
  502. * @read_page_raw: function to read a raw page without ECC. This function
  503. * should hide the specific layout used by the ECC
  504. * controller and always return contiguous in-band and
  505. * out-of-band data even if they're not stored
  506. * contiguously on the NAND chip (e.g.
  507. * NAND_ECC_HW_SYNDROME interleaves in-band and
  508. * out-of-band data).
  509. * @write_page_raw: function to write a raw page without ECC. This function
  510. * should hide the specific layout used by the ECC
  511. * controller and consider the passed data as contiguous
  512. * in-band and out-of-band data. ECC controller is
  513. * responsible for doing the appropriate transformations
  514. * to adapt to its specific layout (e.g.
  515. * NAND_ECC_HW_SYNDROME interleaves in-band and
  516. * out-of-band data).
  517. * @read_page: function to read a page according to the ECC generator
  518. * requirements; returns maximum number of bitflips corrected in
  519. * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
  520. * @read_subpage: function to read parts of the page covered by ECC;
  521. * returns same as read_page()
  522. * @write_subpage: function to write parts of the page covered by ECC.
  523. * @write_page: function to write a page according to the ECC generator
  524. * requirements.
  525. * @write_oob_raw: function to write chip OOB data without ECC
  526. * @read_oob_raw: function to read chip OOB data without ECC
  527. * @read_oob: function to read chip OOB data
  528. * @write_oob: function to write chip OOB data
  529. */
  530. struct nand_ecc_ctrl {
  531. nand_ecc_modes_t mode;
  532. enum nand_ecc_algo algo;
  533. int steps;
  534. int size;
  535. int bytes;
  536. int total;
  537. int strength;
  538. int prepad;
  539. int postpad;
  540. unsigned int options;
  541. struct nand_ecclayout *layout;
  542. void *priv;
  543. void (*hwctl)(struct mtd_info *mtd, int mode);
  544. int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
  545. uint8_t *ecc_code);
  546. int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
  547. uint8_t *calc_ecc);
  548. int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  549. uint8_t *buf, int oob_required, int page);
  550. int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  551. const uint8_t *buf, int oob_required, int page);
  552. int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
  553. uint8_t *buf, int oob_required, int page);
  554. int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  555. uint32_t offs, uint32_t len, uint8_t *buf, int page);
  556. int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
  557. uint32_t offset, uint32_t data_len,
  558. const uint8_t *data_buf, int oob_required, int page);
  559. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  560. const uint8_t *buf, int oob_required, int page);
  561. int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  562. int page);
  563. int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
  564. int page);
  565. int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
  566. int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
  567. int page);
  568. };
  569. static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
  570. {
  571. return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
  572. }
  573. /**
  574. * struct nand_buffers - buffer structure for read/write
  575. * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
  576. * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
  577. * @databuf: buffer pointer for data, size is (page size + oobsize).
  578. *
  579. * Do not change the order of buffers. databuf and oobrbuf must be in
  580. * consecutive order.
  581. */
  582. struct nand_buffers {
  583. uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  584. uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
  585. uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
  586. ARCH_DMA_MINALIGN)];
  587. };
  588. /**
  589. * struct nand_sdr_timings - SDR NAND chip timings
  590. *
  591. * This struct defines the timing requirements of a SDR NAND chip.
  592. * These information can be found in every NAND datasheets and the timings
  593. * meaning are described in the ONFI specifications:
  594. * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
  595. * Parameters)
  596. *
  597. * All these timings are expressed in picoseconds.
  598. *
  599. * @tBERS_max: Block erase time
  600. * @tCCS_min: Change column setup time
  601. * @tPROG_max: Page program time
  602. * @tR_max: Page read time
  603. * @tALH_min: ALE hold time
  604. * @tADL_min: ALE to data loading time
  605. * @tALS_min: ALE setup time
  606. * @tAR_min: ALE to RE# delay
  607. * @tCEA_max: CE# access time
  608. * @tCEH_min: CE# high hold time
  609. * @tCH_min: CE# hold time
  610. * @tCHZ_max: CE# high to output hi-Z
  611. * @tCLH_min: CLE hold time
  612. * @tCLR_min: CLE to RE# delay
  613. * @tCLS_min: CLE setup time
  614. * @tCOH_min: CE# high to output hold
  615. * @tCS_min: CE# setup time
  616. * @tDH_min: Data hold time
  617. * @tDS_min: Data setup time
  618. * @tFEAT_max: Busy time for Set Features and Get Features
  619. * @tIR_min: Output hi-Z to RE# low
  620. * @tITC_max: Interface and Timing Mode Change time
  621. * @tRC_min: RE# cycle time
  622. * @tREA_max: RE# access time
  623. * @tREH_min: RE# high hold time
  624. * @tRHOH_min: RE# high to output hold
  625. * @tRHW_min: RE# high to WE# low
  626. * @tRHZ_max: RE# high to output hi-Z
  627. * @tRLOH_min: RE# low to output hold
  628. * @tRP_min: RE# pulse width
  629. * @tRR_min: Ready to RE# low (data only)
  630. * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
  631. * rising edge of R/B#.
  632. * @tWB_max: WE# high to SR[6] low
  633. * @tWC_min: WE# cycle time
  634. * @tWH_min: WE# high hold time
  635. * @tWHR_min: WE# high to RE# low
  636. * @tWP_min: WE# pulse width
  637. * @tWW_min: WP# transition to WE# low
  638. */
  639. struct nand_sdr_timings {
  640. u64 tBERS_max;
  641. u32 tCCS_min;
  642. u64 tPROG_max;
  643. u64 tR_max;
  644. u32 tALH_min;
  645. u32 tADL_min;
  646. u32 tALS_min;
  647. u32 tAR_min;
  648. u32 tCEA_max;
  649. u32 tCEH_min;
  650. u32 tCH_min;
  651. u32 tCHZ_max;
  652. u32 tCLH_min;
  653. u32 tCLR_min;
  654. u32 tCLS_min;
  655. u32 tCOH_min;
  656. u32 tCS_min;
  657. u32 tDH_min;
  658. u32 tDS_min;
  659. u32 tFEAT_max;
  660. u32 tIR_min;
  661. u32 tITC_max;
  662. u32 tRC_min;
  663. u32 tREA_max;
  664. u32 tREH_min;
  665. u32 tRHOH_min;
  666. u32 tRHW_min;
  667. u32 tRHZ_max;
  668. u32 tRLOH_min;
  669. u32 tRP_min;
  670. u32 tRR_min;
  671. u64 tRST_max;
  672. u32 tWB_max;
  673. u32 tWC_min;
  674. u32 tWH_min;
  675. u32 tWHR_min;
  676. u32 tWP_min;
  677. u32 tWW_min;
  678. };
  679. /**
  680. * enum nand_data_interface_type - NAND interface timing type
  681. * @NAND_SDR_IFACE: Single Data Rate interface
  682. */
  683. enum nand_data_interface_type {
  684. NAND_SDR_IFACE,
  685. };
  686. /**
  687. * struct nand_data_interface - NAND interface timing
  688. * @type: type of the timing
  689. * @timings: The timing, type according to @type
  690. */
  691. struct nand_data_interface {
  692. enum nand_data_interface_type type;
  693. union {
  694. struct nand_sdr_timings sdr;
  695. } timings;
  696. };
  697. /**
  698. * nand_get_sdr_timings - get SDR timing from data interface
  699. * @conf: The data interface
  700. */
  701. static inline const struct nand_sdr_timings *
  702. nand_get_sdr_timings(const struct nand_data_interface *conf)
  703. {
  704. if (conf->type != NAND_SDR_IFACE)
  705. return ERR_PTR(-EINVAL);
  706. return &conf->timings.sdr;
  707. }
  708. /**
  709. * struct nand_chip - NAND Private Flash Chip Data
  710. * @mtd: MTD device registered to the MTD framework
  711. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
  712. * flash device
  713. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
  714. * flash device.
  715. * @flash_node: [BOARDSPECIFIC] device node describing this instance
  716. * @read_byte: [REPLACEABLE] read one byte from the chip
  717. * @read_word: [REPLACEABLE] read one word from the chip
  718. * @write_byte: [REPLACEABLE] write a single byte to the chip on the
  719. * low 8 I/O lines
  720. * @write_buf: [REPLACEABLE] write data from the buffer to the chip
  721. * @read_buf: [REPLACEABLE] read data from the chip into the buffer
  722. * @select_chip: [REPLACEABLE] select chip nr
  723. * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
  724. * @block_markbad: [REPLACEABLE] mark a block bad
  725. * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
  726. * ALE/CLE/nCE. Also used to write command and address
  727. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
  728. * device ready/busy line. If set to NULL no access to
  729. * ready/busy is available and the ready/busy information
  730. * is read from the chip status register.
  731. * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
  732. * commands to the chip.
  733. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
  734. * ready.
  735. * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
  736. * setting the read-retry mode. Mostly needed for MLC NAND.
  737. * @ecc: [BOARDSPECIFIC] ECC control structure
  738. * @buffers: buffer structure for read/write
  739. * @buf_align: minimum buffer alignment required by a platform
  740. * @hwcontrol: platform-specific hardware control structure
  741. * @erase: [REPLACEABLE] erase function
  742. * @scan_bbt: [REPLACEABLE] function to scan bad block table
  743. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
  744. * data from array to read regs (tR).
  745. * @state: [INTERN] the current state of the NAND device
  746. * @oob_poi: "poison value buffer," used for laying out OOB data
  747. * before writing
  748. * @page_shift: [INTERN] number of address bits in a page (column
  749. * address bits).
  750. * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
  751. * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
  752. * @chip_shift: [INTERN] number of address bits in one chip
  753. * @options: [BOARDSPECIFIC] various chip options. They can partly
  754. * be set to inform nand_scan about special functionality.
  755. * See the defines for further explanation.
  756. * @bbt_options: [INTERN] bad block specific options. All options used
  757. * here must come from bbm.h. By default, these options
  758. * will be copied to the appropriate nand_bbt_descr's.
  759. * @badblockpos: [INTERN] position of the bad block marker in the oob
  760. * area.
  761. * @badblockbits: [INTERN] minimum number of set bits in a good block's
  762. * bad block marker position; i.e., BBM == 11110111b is
  763. * not bad when badblockbits == 7
  764. * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
  765. * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
  766. * Minimum amount of bit errors per @ecc_step_ds guaranteed
  767. * to be correctable. If unknown, set to zero.
  768. * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
  769. * also from the datasheet. It is the recommended ECC step
  770. * size, if known; if unknown, set to zero.
  771. * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
  772. * set to the actually used ONFI mode if the chip is
  773. * ONFI compliant or deduced from the datasheet if
  774. * the NAND chip is not ONFI compliant.
  775. * @numchips: [INTERN] number of physical chips
  776. * @chipsize: [INTERN] the size of one chip for multichip arrays
  777. * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
  778. * @pagebuf: [INTERN] holds the pagenumber which is currently in
  779. * data_buf.
  780. * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
  781. * currently in data_buf.
  782. * @subpagesize: [INTERN] holds the subpagesize
  783. * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
  784. * non 0 if ONFI supported.
  785. * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
  786. * non 0 if JEDEC supported.
  787. * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
  788. * supported, 0 otherwise.
  789. * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
  790. * supported, 0 otherwise.
  791. * @read_retries: [INTERN] the number of read retry modes supported
  792. * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
  793. * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
  794. * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
  795. * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
  796. * means the configuration should not be applied but
  797. * only checked.
  798. * @bbt: [INTERN] bad block table pointer
  799. * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
  800. * lookup.
  801. * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
  802. * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
  803. * bad block scan.
  804. * @controller: [REPLACEABLE] a pointer to a hardware controller
  805. * structure which is shared among multiple independent
  806. * devices.
  807. * @priv: [OPTIONAL] pointer to private chip data
  808. * @write_page: [REPLACEABLE] High-level page write function
  809. */
  810. struct nand_chip {
  811. struct mtd_info mtd;
  812. void __iomem *IO_ADDR_R;
  813. void __iomem *IO_ADDR_W;
  814. int flash_node;
  815. uint8_t (*read_byte)(struct mtd_info *mtd);
  816. u16 (*read_word)(struct mtd_info *mtd);
  817. void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
  818. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  819. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  820. void (*select_chip)(struct mtd_info *mtd, int chip);
  821. int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
  822. int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  823. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  824. int (*dev_ready)(struct mtd_info *mtd);
  825. void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
  826. int page_addr);
  827. int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  828. int (*erase)(struct mtd_info *mtd, int page);
  829. int (*scan_bbt)(struct mtd_info *mtd);
  830. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  831. uint32_t offset, int data_len, const uint8_t *buf,
  832. int oob_required, int page, int raw);
  833. int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
  834. int feature_addr, uint8_t *subfeature_para);
  835. int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
  836. int feature_addr, uint8_t *subfeature_para);
  837. int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
  838. int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
  839. const struct nand_data_interface *conf);
  840. int chip_delay;
  841. unsigned int options;
  842. unsigned int bbt_options;
  843. int page_shift;
  844. int phys_erase_shift;
  845. int bbt_erase_shift;
  846. int chip_shift;
  847. int numchips;
  848. uint64_t chipsize;
  849. int pagemask;
  850. int pagebuf;
  851. unsigned int pagebuf_bitflips;
  852. int subpagesize;
  853. uint8_t bits_per_cell;
  854. uint16_t ecc_strength_ds;
  855. uint16_t ecc_step_ds;
  856. int onfi_timing_mode_default;
  857. int badblockpos;
  858. int badblockbits;
  859. int onfi_version;
  860. int jedec_version;
  861. struct nand_onfi_params onfi_params;
  862. struct nand_jedec_params jedec_params;
  863. struct nand_data_interface *data_interface;
  864. int read_retries;
  865. flstate_t state;
  866. uint8_t *oob_poi;
  867. struct nand_hw_control *controller;
  868. struct nand_ecclayout *ecclayout;
  869. struct nand_ecc_ctrl ecc;
  870. struct nand_buffers *buffers;
  871. unsigned long buf_align;
  872. struct nand_hw_control hwcontrol;
  873. uint8_t *bbt;
  874. struct nand_bbt_descr *bbt_td;
  875. struct nand_bbt_descr *bbt_md;
  876. struct nand_bbt_descr *badblock_pattern;
  877. void *priv;
  878. };
  879. static inline void nand_set_flash_node(struct nand_chip *chip,
  880. ofnode node)
  881. {
  882. chip->flash_node = ofnode_to_offset(node);
  883. }
  884. static inline ofnode nand_get_flash_node(struct nand_chip *chip)
  885. {
  886. return offset_to_ofnode(chip->flash_node);
  887. }
  888. static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
  889. {
  890. return container_of(mtd, struct nand_chip, mtd);
  891. }
  892. static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
  893. {
  894. return &chip->mtd;
  895. }
  896. static inline void *nand_get_controller_data(struct nand_chip *chip)
  897. {
  898. return chip->priv;
  899. }
  900. static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
  901. {
  902. chip->priv = priv;
  903. }
  904. /*
  905. * NAND Flash Manufacturer ID Codes
  906. */
  907. #define NAND_MFR_TOSHIBA 0x98
  908. #define NAND_MFR_SAMSUNG 0xec
  909. #define NAND_MFR_FUJITSU 0x04
  910. #define NAND_MFR_NATIONAL 0x8f
  911. #define NAND_MFR_RENESAS 0x07
  912. #define NAND_MFR_STMICRO 0x20
  913. #define NAND_MFR_HYNIX 0xad
  914. #define NAND_MFR_MICRON 0x2c
  915. #define NAND_MFR_AMD 0x01
  916. #define NAND_MFR_MACRONIX 0xc2
  917. #define NAND_MFR_EON 0x92
  918. #define NAND_MFR_SANDISK 0x45
  919. #define NAND_MFR_INTEL 0x89
  920. #define NAND_MFR_ATO 0x9b
  921. /* The maximum expected count of bytes in the NAND ID sequence */
  922. #define NAND_MAX_ID_LEN 8
  923. /*
  924. * A helper for defining older NAND chips where the second ID byte fully
  925. * defined the chip, including the geometry (chip size, eraseblock size, page
  926. * size). All these chips have 512 bytes NAND page size.
  927. */
  928. #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
  929. { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
  930. .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
  931. /*
  932. * A helper for defining newer chips which report their page size and
  933. * eraseblock size via the extended ID bytes.
  934. *
  935. * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
  936. * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
  937. * device ID now only represented a particular total chip size (and voltage,
  938. * buswidth), and the page size, eraseblock size, and OOB size could vary while
  939. * using the same device ID.
  940. */
  941. #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
  942. { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
  943. .options = (opts) }
  944. #define NAND_ECC_INFO(_strength, _step) \
  945. { .strength_ds = (_strength), .step_ds = (_step) }
  946. #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
  947. #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
  948. /**
  949. * struct nand_flash_dev - NAND Flash Device ID Structure
  950. * @name: a human-readable name of the NAND chip
  951. * @dev_id: the device ID (the second byte of the full chip ID array)
  952. * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
  953. * memory address as @id[0])
  954. * @dev_id: device ID part of the full chip ID array (refers the same memory
  955. * address as @id[1])
  956. * @id: full device ID array
  957. * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
  958. * well as the eraseblock size) is determined from the extended NAND
  959. * chip ID array)
  960. * @chipsize: total chip size in MiB
  961. * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
  962. * @options: stores various chip bit options
  963. * @id_len: The valid length of the @id.
  964. * @oobsize: OOB size
  965. * @ecc: ECC correctability and step information from the datasheet.
  966. * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
  967. * @ecc_strength_ds in nand_chip{}.
  968. * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
  969. * @ecc_step_ds in nand_chip{}, also from the datasheet.
  970. * For example, the "4bit ECC for each 512Byte" can be set with
  971. * NAND_ECC_INFO(4, 512).
  972. * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
  973. * reset. Should be deduced from timings described
  974. * in the datasheet.
  975. *
  976. */
  977. struct nand_flash_dev {
  978. char *name;
  979. union {
  980. struct {
  981. uint8_t mfr_id;
  982. uint8_t dev_id;
  983. };
  984. uint8_t id[NAND_MAX_ID_LEN];
  985. };
  986. unsigned int pagesize;
  987. unsigned int chipsize;
  988. unsigned int erasesize;
  989. unsigned int options;
  990. uint16_t id_len;
  991. uint16_t oobsize;
  992. struct {
  993. uint16_t strength_ds;
  994. uint16_t step_ds;
  995. } ecc;
  996. int onfi_timing_mode_default;
  997. };
  998. /**
  999. * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  1000. * @name: Manufacturer name
  1001. * @id: manufacturer ID code of device.
  1002. */
  1003. struct nand_manufacturers {
  1004. int id;
  1005. char *name;
  1006. };
  1007. extern struct nand_flash_dev nand_flash_ids[];
  1008. extern struct nand_manufacturers nand_manuf_ids[];
  1009. int nand_default_bbt(struct mtd_info *mtd);
  1010. int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
  1011. int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
  1012. int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  1013. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  1014. int allowbbt);
  1015. int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  1016. size_t *retlen, uint8_t *buf);
  1017. /*
  1018. * Constants for oob configuration
  1019. */
  1020. #define NAND_SMALL_BADBLOCK_POS 5
  1021. #define NAND_LARGE_BADBLOCK_POS 0
  1022. /**
  1023. * struct platform_nand_chip - chip level device structure
  1024. * @nr_chips: max. number of chips to scan for
  1025. * @chip_offset: chip number offset
  1026. * @nr_partitions: number of partitions pointed to by partitions (or zero)
  1027. * @partitions: mtd partition list
  1028. * @chip_delay: R/B delay value in us
  1029. * @options: Option flags, e.g. 16bit buswidth
  1030. * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
  1031. * @part_probe_types: NULL-terminated array of probe types
  1032. */
  1033. struct platform_nand_chip {
  1034. int nr_chips;
  1035. int chip_offset;
  1036. int nr_partitions;
  1037. struct mtd_partition *partitions;
  1038. int chip_delay;
  1039. unsigned int options;
  1040. unsigned int bbt_options;
  1041. const char **part_probe_types;
  1042. };
  1043. /* Keep gcc happy */
  1044. struct platform_device;
  1045. /**
  1046. * struct platform_nand_ctrl - controller level device structure
  1047. * @probe: platform specific function to probe/setup hardware
  1048. * @remove: platform specific function to remove/teardown hardware
  1049. * @hwcontrol: platform specific hardware control structure
  1050. * @dev_ready: platform specific function to read ready/busy pin
  1051. * @select_chip: platform specific chip select function
  1052. * @cmd_ctrl: platform specific function for controlling
  1053. * ALE/CLE/nCE. Also used to write command and address
  1054. * @write_buf: platform specific function for write buffer
  1055. * @read_buf: platform specific function for read buffer
  1056. * @read_byte: platform specific function to read one byte from chip
  1057. * @priv: private data to transport driver specific settings
  1058. *
  1059. * All fields are optional and depend on the hardware driver requirements
  1060. */
  1061. struct platform_nand_ctrl {
  1062. int (*probe)(struct platform_device *pdev);
  1063. void (*remove)(struct platform_device *pdev);
  1064. void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  1065. int (*dev_ready)(struct mtd_info *mtd);
  1066. void (*select_chip)(struct mtd_info *mtd, int chip);
  1067. void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
  1068. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  1069. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  1070. unsigned char (*read_byte)(struct mtd_info *mtd);
  1071. void *priv;
  1072. };
  1073. /**
  1074. * struct platform_nand_data - container structure for platform-specific data
  1075. * @chip: chip level chip structure
  1076. * @ctrl: controller level device structure
  1077. */
  1078. struct platform_nand_data {
  1079. struct platform_nand_chip chip;
  1080. struct platform_nand_ctrl ctrl;
  1081. };
  1082. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  1083. /* return the supported features. */
  1084. static inline int onfi_feature(struct nand_chip *chip)
  1085. {
  1086. return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
  1087. }
  1088. /* return the supported asynchronous timing mode. */
  1089. static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  1090. {
  1091. if (!chip->onfi_version)
  1092. return ONFI_TIMING_MODE_UNKNOWN;
  1093. return le16_to_cpu(chip->onfi_params.async_timing_mode);
  1094. }
  1095. /* return the supported synchronous timing mode. */
  1096. static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  1097. {
  1098. if (!chip->onfi_version)
  1099. return ONFI_TIMING_MODE_UNKNOWN;
  1100. return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
  1101. }
  1102. #else
  1103. static inline int onfi_feature(struct nand_chip *chip)
  1104. {
  1105. return 0;
  1106. }
  1107. static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
  1108. {
  1109. return ONFI_TIMING_MODE_UNKNOWN;
  1110. }
  1111. static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
  1112. {
  1113. return ONFI_TIMING_MODE_UNKNOWN;
  1114. }
  1115. #endif
  1116. int onfi_init_data_interface(struct nand_chip *chip,
  1117. struct nand_data_interface *iface,
  1118. enum nand_data_interface_type type,
  1119. int timing_mode);
  1120. /*
  1121. * Check if it is a SLC nand.
  1122. * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
  1123. * We do not distinguish the MLC and TLC now.
  1124. */
  1125. static inline bool nand_is_slc(struct nand_chip *chip)
  1126. {
  1127. return chip->bits_per_cell == 1;
  1128. }
  1129. /**
  1130. * Check if the opcode's address should be sent only on the lower 8 bits
  1131. * @command: opcode to check
  1132. */
  1133. static inline int nand_opcode_8bits(unsigned int command)
  1134. {
  1135. switch (command) {
  1136. case NAND_CMD_READID:
  1137. case NAND_CMD_PARAM:
  1138. case NAND_CMD_GET_FEATURES:
  1139. case NAND_CMD_SET_FEATURES:
  1140. return 1;
  1141. default:
  1142. break;
  1143. }
  1144. return 0;
  1145. }
  1146. /* return the supported JEDEC features. */
  1147. static inline int jedec_feature(struct nand_chip *chip)
  1148. {
  1149. return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
  1150. : 0;
  1151. }
  1152. /* Standard NAND functions from nand_base.c */
  1153. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
  1154. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
  1155. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
  1156. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
  1157. uint8_t nand_read_byte(struct mtd_info *mtd);
  1158. /* get timing characteristics from ONFI timing mode. */
  1159. const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
  1160. /* get data interface from ONFI timing mode 0, used after reset. */
  1161. const struct nand_data_interface *nand_get_default_data_interface(void);
  1162. int nand_check_erased_ecc_chunk(void *data, int datalen,
  1163. void *ecc, int ecclen,
  1164. void *extraoob, int extraooblen,
  1165. int threshold);
  1166. int nand_check_ecc_caps(struct nand_chip *chip,
  1167. const struct nand_ecc_caps *caps, int oobavail);
  1168. int nand_match_ecc_req(struct nand_chip *chip,
  1169. const struct nand_ecc_caps *caps, int oobavail);
  1170. int nand_maximize_ecc(struct nand_chip *chip,
  1171. const struct nand_ecc_caps *caps, int oobavail);
  1172. /* Reset and initialize a NAND device */
  1173. int nand_reset(struct nand_chip *chip, int chipnr);
  1174. /* NAND operation helpers */
  1175. int nand_reset_op(struct nand_chip *chip);
  1176. int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
  1177. unsigned int len);
  1178. int nand_status_op(struct nand_chip *chip, u8 *status);
  1179. int nand_exit_status_op(struct nand_chip *chip);
  1180. int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
  1181. int nand_read_page_op(struct nand_chip *chip, unsigned int page,
  1182. unsigned int offset_in_page, void *buf, unsigned int len);
  1183. int nand_change_read_column_op(struct nand_chip *chip,
  1184. unsigned int offset_in_page, void *buf,
  1185. unsigned int len, bool force_8bit);
  1186. int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
  1187. unsigned int offset_in_page, void *buf, unsigned int len);
  1188. int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
  1189. unsigned int offset_in_page, const void *buf,
  1190. unsigned int len);
  1191. int nand_prog_page_end_op(struct nand_chip *chip);
  1192. int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
  1193. unsigned int offset_in_page, const void *buf,
  1194. unsigned int len);
  1195. int nand_change_write_column_op(struct nand_chip *chip,
  1196. unsigned int offset_in_page, const void *buf,
  1197. unsigned int len, bool force_8bit);
  1198. int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
  1199. bool force_8bit);
  1200. int nand_write_data_op(struct nand_chip *chip, const void *buf,
  1201. unsigned int len, bool force_8bit);
  1202. #endif /* __LINUX_MTD_RAWNAND_H */