drm_dp_helper.h 14 KB

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  1. /*
  2. * Copyright © 2008 Keith Packard
  3. *
  4. * Permission to use, copy, modify, distribute, and sell this software and its
  5. * documentation for any purpose is hereby granted without fee, provided that
  6. * the above copyright notice appear in all copies and that both that copyright
  7. * notice and this permission notice appear in supporting documentation, and
  8. * that the name of the copyright holders not be used in advertising or
  9. * publicity pertaining to distribution of the software without specific,
  10. * written prior permission. The copyright holders make no representations
  11. * about the suitability of this software for any purpose. It is provided "as
  12. * is" without express or implied warranty.
  13. *
  14. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20. * OF THIS SOFTWARE.
  21. */
  22. #ifndef _DRM_DP_HELPER_H_
  23. #define _DRM_DP_HELPER_H_
  24. /*
  25. * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
  26. * DP and DPCD versions are independent. Differences from 1.0 are not noted,
  27. * 1.0 devices basically don't exist in the wild.
  28. *
  29. * Abbreviations, in chronological order:
  30. *
  31. * eDP: Embedded DisplayPort version 1
  32. * DPI: DisplayPort Interoperability Guideline v1.1a
  33. * 1.2: DisplayPort 1.2
  34. * MST: Multistream Transport - part of DP 1.2a
  35. *
  36. * 1.2 formally includes both eDP and DPI definitions.
  37. */
  38. #define DP_AUX_I2C_WRITE 0x0
  39. #define DP_AUX_I2C_READ 0x1
  40. #define DP_AUX_I2C_STATUS 0x2
  41. #define DP_AUX_I2C_MOT 0x4
  42. #define DP_AUX_NATIVE_WRITE 0x8
  43. #define DP_AUX_NATIVE_READ 0x9
  44. #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
  45. #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
  46. #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
  47. #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
  48. #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
  49. #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
  50. #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
  51. #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
  52. /* AUX CH addresses */
  53. /* DPCD */
  54. #define DP_DPCD_REV 0x000
  55. #define DP_MAX_LINK_RATE 0x001
  56. #define DP_MAX_LANE_COUNT 0x002
  57. # define DP_MAX_LANE_COUNT_MASK 0x1f
  58. # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
  59. # define DP_ENHANCED_FRAME_CAP (1 << 7)
  60. #define DP_MAX_DOWNSPREAD 0x003
  61. # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
  62. #define DP_NORP 0x004
  63. #define DP_DOWNSTREAMPORT_PRESENT 0x005
  64. # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
  65. # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
  66. # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
  67. # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
  68. # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
  69. # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
  70. # define DP_FORMAT_CONVERSION (1 << 3)
  71. # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
  72. #define DP_MAIN_LINK_CHANNEL_CODING 0x006
  73. #define DP_DOWN_STREAM_PORT_COUNT 0x007
  74. # define DP_PORT_COUNT_MASK 0x0f
  75. # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
  76. # define DP_OUI_SUPPORT (1 << 7)
  77. #define DP_I2C_SPEED_CAP 0x00c /* DPI */
  78. # define DP_I2C_SPEED_1K 0x01
  79. # define DP_I2C_SPEED_5K 0x02
  80. # define DP_I2C_SPEED_10K 0x04
  81. # define DP_I2C_SPEED_100K 0x08
  82. # define DP_I2C_SPEED_400K 0x10
  83. # define DP_I2C_SPEED_1M 0x20
  84. #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
  85. #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
  86. /* Multiple stream transport */
  87. #define DP_FAUX_CAP 0x020 /* 1.2 */
  88. # define DP_FAUX_CAP_1 (1 << 0)
  89. #define DP_MSTM_CAP 0x021 /* 1.2 */
  90. # define DP_MST_CAP (1 << 0)
  91. #define DP_GUID 0x030 /* 1.2 */
  92. #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
  93. # define DP_PSR_IS_SUPPORTED 1
  94. #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
  95. # define DP_PSR_NO_TRAIN_ON_EXIT 1
  96. # define DP_PSR_SETUP_TIME_330 (0 << 1)
  97. # define DP_PSR_SETUP_TIME_275 (1 << 1)
  98. # define DP_PSR_SETUP_TIME_220 (2 << 1)
  99. # define DP_PSR_SETUP_TIME_165 (3 << 1)
  100. # define DP_PSR_SETUP_TIME_110 (4 << 1)
  101. # define DP_PSR_SETUP_TIME_55 (5 << 1)
  102. # define DP_PSR_SETUP_TIME_0 (6 << 1)
  103. # define DP_PSR_SETUP_TIME_MASK (7 << 1)
  104. # define DP_PSR_SETUP_TIME_SHIFT 1
  105. /*
  106. * 0x80-0x8f describe downstream port capabilities, but there are two layouts
  107. * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
  108. * each port's descriptor is one byte wide. If it was set, each port's is
  109. * four bytes wide, starting with the one byte from the base info. As of
  110. * DP interop v1.1a only VGA defines additional detail.
  111. */
  112. /* offset 0 */
  113. #define DP_DOWNSTREAM_PORT_0 0x80
  114. # define DP_DS_PORT_TYPE_MASK (7 << 0)
  115. # define DP_DS_PORT_TYPE_DP 0
  116. # define DP_DS_PORT_TYPE_VGA 1
  117. # define DP_DS_PORT_TYPE_DVI 2
  118. # define DP_DS_PORT_TYPE_HDMI 3
  119. # define DP_DS_PORT_TYPE_NON_EDID 4
  120. # define DP_DS_PORT_HPD (1 << 3)
  121. /* offset 1 for VGA is maximum megapixels per second / 8 */
  122. /* offset 2 */
  123. # define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
  124. # define DP_DS_VGA_8BPC 0
  125. # define DP_DS_VGA_10BPC 1
  126. # define DP_DS_VGA_12BPC 2
  127. # define DP_DS_VGA_16BPC 3
  128. /* link configuration */
  129. #define DP_LINK_BW_SET 0x100
  130. # define DP_LINK_BW_1_62 0x06
  131. # define DP_LINK_BW_2_7 0x0a
  132. # define DP_LINK_BW_5_4 0x14 /* 1.2 */
  133. #define DP_LANE_COUNT_SET 0x101
  134. # define DP_LANE_COUNT_MASK 0x0f
  135. # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
  136. #define DP_TRAINING_PATTERN_SET 0x102
  137. # define DP_TRAINING_PATTERN_DISABLE 0
  138. # define DP_TRAINING_PATTERN_1 1
  139. # define DP_TRAINING_PATTERN_2 2
  140. # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
  141. # define DP_TRAINING_PATTERN_MASK 0x3
  142. # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
  143. # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
  144. # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
  145. # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
  146. # define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
  147. # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
  148. # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
  149. # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
  150. # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
  151. # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
  152. # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
  153. #define DP_TRAINING_LANE0_SET 0x103
  154. #define DP_TRAINING_LANE1_SET 0x104
  155. #define DP_TRAINING_LANE2_SET 0x105
  156. #define DP_TRAINING_LANE3_SET 0x106
  157. # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
  158. # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
  159. # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
  160. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
  161. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
  162. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
  163. # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
  164. # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
  165. # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
  166. # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
  167. # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
  168. # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
  169. # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
  170. # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
  171. #define DP_DOWNSPREAD_CTRL 0x107
  172. # define DP_SPREAD_AMP_0_5 (1 << 4)
  173. # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
  174. #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
  175. # define DP_SET_ANSI_8B10B (1 << 0)
  176. #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
  177. /* bitmask as for DP_I2C_SPEED_CAP */
  178. #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
  179. #define DP_MSTM_CTRL 0x111 /* 1.2 */
  180. # define DP_MST_EN (1 << 0)
  181. # define DP_UP_REQ_EN (1 << 1)
  182. # define DP_UPSTREAM_IS_SRC (1 << 2)
  183. #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
  184. # define DP_PSR_ENABLE (1 << 0)
  185. # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
  186. # define DP_PSR_CRC_VERIFICATION (1 << 2)
  187. # define DP_PSR_FRAME_CAPTURE (1 << 3)
  188. #define DP_ADAPTER_CTRL 0x1a0
  189. # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
  190. #define DP_BRANCH_DEVICE_CTRL 0x1a1
  191. # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
  192. #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
  193. #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
  194. #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
  195. #define DP_SINK_COUNT 0x200
  196. /* prior to 1.2 bit 7 was reserved mbz */
  197. # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
  198. # define DP_SINK_CP_READY (1 << 6)
  199. #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
  200. # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
  201. # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
  202. # define DP_CP_IRQ (1 << 2)
  203. # define DP_MCCS_IRQ (1 << 3)
  204. # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
  205. # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
  206. # define DP_SINK_SPECIFIC_IRQ (1 << 6)
  207. #define DP_LANE0_1_STATUS 0x202
  208. #define DP_LANE2_3_STATUS 0x203
  209. # define DP_LANE_CR_DONE (1 << 0)
  210. # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
  211. # define DP_LANE_SYMBOL_LOCKED (1 << 2)
  212. #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
  213. DP_LANE_CHANNEL_EQ_DONE | \
  214. DP_LANE_SYMBOL_LOCKED)
  215. #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
  216. #define DP_INTERLANE_ALIGN_DONE (1 << 0)
  217. #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
  218. #define DP_LINK_STATUS_UPDATED (1 << 7)
  219. #define DP_SINK_STATUS 0x205
  220. #define DP_SINK_STATUS_PORT0_IN_SYNC (1 << 0)
  221. #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
  222. #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
  223. #define DP_ADJUST_REQUEST_LANE0_1 0x206
  224. #define DP_ADJUST_REQUEST_LANE2_3 0x207
  225. # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
  226. # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
  227. # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
  228. # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
  229. # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
  230. # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
  231. # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
  232. # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
  233. #define DP_TEST_REQUEST 0x218
  234. # define DP_TEST_LINK_TRAINING (1 << 0)
  235. # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
  236. # define DP_TEST_LINK_EDID_READ (1 << 2)
  237. # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
  238. # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
  239. #define DP_TEST_LINK_RATE 0x219
  240. # define DP_LINK_RATE_162 (0x6)
  241. # define DP_LINK_RATE_27 (0xa)
  242. #define DP_TEST_LANE_COUNT 0x220
  243. #define DP_TEST_PATTERN 0x221
  244. #define DP_TEST_CRC_R_CR 0x240
  245. #define DP_TEST_CRC_G_Y 0x242
  246. #define DP_TEST_CRC_B_CB 0x244
  247. #define DP_TEST_SINK_MISC 0x246
  248. #define DP_TEST_CRC_SUPPORTED (1 << 5)
  249. #define DP_TEST_RESPONSE 0x260
  250. # define DP_TEST_ACK (1 << 0)
  251. # define DP_TEST_NAK (1 << 1)
  252. # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
  253. #define DP_TEST_EDID_CHECKSUM 0x261
  254. #define DP_TEST_SINK 0x270
  255. #define DP_TEST_SINK_START (1 << 0)
  256. #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
  257. # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
  258. # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
  259. #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
  260. /* up to ID_SLOT_63 at 0x2ff */
  261. #define DP_SOURCE_OUI 0x300
  262. #define DP_SINK_OUI 0x400
  263. #define DP_BRANCH_OUI 0x500
  264. #define DP_SET_POWER 0x600
  265. # define DP_SET_POWER_D0 0x1
  266. # define DP_SET_POWER_D3 0x2
  267. # define DP_SET_POWER_MASK 0x3
  268. #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
  269. #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
  270. #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
  271. #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
  272. #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
  273. /* 0-5 sink count */
  274. # define DP_SINK_COUNT_CP_READY (1 << 6)
  275. #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
  276. #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
  277. #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
  278. #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
  279. # define DP_PSR_LINK_CRC_ERROR (1 << 0)
  280. # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
  281. #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
  282. # define DP_PSR_CAPS_CHANGE (1 << 0)
  283. #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
  284. # define DP_PSR_SINK_INACTIVE 0
  285. # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
  286. # define DP_PSR_SINK_ACTIVE_RFB 2
  287. # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
  288. # define DP_PSR_SINK_ACTIVE_RESYNC 4
  289. # define DP_PSR_SINK_INTERNAL_ERROR 7
  290. # define DP_PSR_SINK_STATE_MASK 0x07
  291. /* DP 1.2 Sideband message defines */
  292. /* peer device type - DP 1.2a Table 2-92 */
  293. #define DP_PEER_DEVICE_NONE 0x0
  294. #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
  295. #define DP_PEER_DEVICE_MST_BRANCHING 0x2
  296. #define DP_PEER_DEVICE_SST_SINK 0x3
  297. #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
  298. /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
  299. #define DP_LINK_ADDRESS 0x01
  300. #define DP_CONNECTION_STATUS_NOTIFY 0x02
  301. #define DP_ENUM_PATH_RESOURCES 0x10
  302. #define DP_ALLOCATE_PAYLOAD 0x11
  303. #define DP_QUERY_PAYLOAD 0x12
  304. #define DP_RESOURCE_STATUS_NOTIFY 0x13
  305. #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
  306. #define DP_REMOTE_DPCD_READ 0x20
  307. #define DP_REMOTE_DPCD_WRITE 0x21
  308. #define DP_REMOTE_I2C_READ 0x22
  309. #define DP_REMOTE_I2C_WRITE 0x23
  310. #define DP_POWER_UP_PHY 0x24
  311. #define DP_POWER_DOWN_PHY 0x25
  312. #define DP_SINK_EVENT_NOTIFY 0x30
  313. #define DP_QUERY_STREAM_ENC_STATUS 0x38
  314. /* DP 1.2 MST sideband nak reasons - table 2.84 */
  315. #define DP_NAK_WRITE_FAILURE 0x01
  316. #define DP_NAK_INVALID_READ 0x02
  317. #define DP_NAK_CRC_FAILURE 0x03
  318. #define DP_NAK_BAD_PARAM 0x04
  319. #define DP_NAK_DEFER 0x05
  320. #define DP_NAK_LINK_FAILURE 0x06
  321. #define DP_NAK_NO_RESOURCES 0x07
  322. #define DP_NAK_DPCD_FAIL 0x08
  323. #define DP_NAK_I2C_NAK 0x09
  324. #define DP_NAK_ALLOCATE_FAIL 0x0a
  325. #define MODE_I2C_START 1
  326. #define MODE_I2C_WRITE 2
  327. #define MODE_I2C_READ 4
  328. #define MODE_I2C_STOP 8
  329. /* Rest of file omitted as it is not used in U-Boot */
  330. #endif /* _DRM_DP_HELPER_H_ */