imx_lpi2c.h 33 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductors, Inc.
  4. *
  5. * I2CLP driver for i.MX
  6. *
  7. */
  8. #ifndef __IMX_LPI2C_H__
  9. #define __IMX_LPI2C_H__
  10. #include <clk.h>
  11. struct imx_lpi2c_bus {
  12. int index;
  13. ulong base;
  14. ulong driver_data;
  15. int speed;
  16. struct i2c_pads_info *pads_info;
  17. struct udevice *bus;
  18. struct clk per_clk;
  19. struct clk ipg_clk;
  20. };
  21. struct imx_lpi2c_reg {
  22. u32 verid;
  23. u32 param;
  24. u8 reserved_0[8];
  25. u32 mcr;
  26. u32 msr;
  27. u32 mier;
  28. u32 mder;
  29. u32 mcfgr0;
  30. u32 mcfgr1;
  31. u32 mcfgr2;
  32. u32 mcfgr3;
  33. u8 reserved_1[16];
  34. u32 mdmr;
  35. u8 reserved_2[4];
  36. u32 mccr0;
  37. u8 reserved_3[4];
  38. u32 mccr1;
  39. u8 reserved_4[4];
  40. u32 mfcr;
  41. u32 mfsr;
  42. u32 mtdr;
  43. u8 reserved_5[12];
  44. u32 mrdr;
  45. u8 reserved_6[156];
  46. u32 scr;
  47. u32 ssr;
  48. u32 sier;
  49. u32 sder;
  50. u8 reserved_7[4];
  51. u32 scfgr1;
  52. u32 scfgr2;
  53. u8 reserved_8[20];
  54. u32 samr;
  55. u8 reserved_9[12];
  56. u32 sasr;
  57. u32 star;
  58. u8 reserved_10[8];
  59. u32 stdr;
  60. u8 reserved_11[12];
  61. u32 srdr;
  62. };
  63. typedef enum lpi2c_status {
  64. LPI2C_SUCESS = 0,
  65. LPI2C_END_PACKET_ERR,
  66. LPI2C_STOP_ERR,
  67. LPI2C_NAK_ERR,
  68. LPI2C_ARB_LOST_ERR,
  69. LPI2C_FIFO_ERR,
  70. LPI2C_PIN_LOW_TIMEOUT_ERR,
  71. LPI2C_DATA_MATCH_ERR,
  72. LPI2C_BUSY,
  73. LPI2C_IDLE,
  74. LPI2C_BIT_ERR,
  75. LPI2C_NO_TRANS_PROG,
  76. LPI2C_DMA_REQ_FAIL,
  77. } lpi2c_status_t;
  78. /* ----------------------------------------------------------------------------
  79. -- LPI2C Register Masks
  80. ---------------------------------------------------------------------------- */
  81. /*!
  82. * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
  83. * @{
  84. */
  85. /*! @name VERID - Version ID Register */
  86. #define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
  87. #define LPI2C_VERID_FEATURE_SHIFT (0U)
  88. #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
  89. #define LPI2C_VERID_MINOR_MASK (0xFF0000U)
  90. #define LPI2C_VERID_MINOR_SHIFT (16U)
  91. #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
  92. #define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
  93. #define LPI2C_VERID_MAJOR_SHIFT (24U)
  94. #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
  95. /*! @name PARAM - Parameter Register */
  96. #define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
  97. #define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
  98. #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
  99. #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
  100. #define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
  101. #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
  102. /*! @name MCR - Master Control Register */
  103. #define LPI2C_MCR_MEN_MASK (0x1U)
  104. #define LPI2C_MCR_MEN_SHIFT (0U)
  105. #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
  106. #define LPI2C_MCR_RST_MASK (0x2U)
  107. #define LPI2C_MCR_RST_SHIFT (1U)
  108. #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
  109. #define LPI2C_MCR_DOZEN_MASK (0x4U)
  110. #define LPI2C_MCR_DOZEN_SHIFT (2U)
  111. #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
  112. #define LPI2C_MCR_DBGEN_MASK (0x8U)
  113. #define LPI2C_MCR_DBGEN_SHIFT (3U)
  114. #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
  115. #define LPI2C_MCR_RTF_MASK (0x100U)
  116. #define LPI2C_MCR_RTF_SHIFT (8U)
  117. #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
  118. #define LPI2C_MCR_RRF_MASK (0x200U)
  119. #define LPI2C_MCR_RRF_SHIFT (9U)
  120. #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
  121. /*! @name MSR - Master Status Register */
  122. #define LPI2C_MSR_TDF_MASK (0x1U)
  123. #define LPI2C_MSR_TDF_SHIFT (0U)
  124. #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
  125. #define LPI2C_MSR_RDF_MASK (0x2U)
  126. #define LPI2C_MSR_RDF_SHIFT (1U)
  127. #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
  128. #define LPI2C_MSR_EPF_MASK (0x100U)
  129. #define LPI2C_MSR_EPF_SHIFT (8U)
  130. #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
  131. #define LPI2C_MSR_SDF_MASK (0x200U)
  132. #define LPI2C_MSR_SDF_SHIFT (9U)
  133. #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
  134. #define LPI2C_MSR_NDF_MASK (0x400U)
  135. #define LPI2C_MSR_NDF_SHIFT (10U)
  136. #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
  137. #define LPI2C_MSR_ALF_MASK (0x800U)
  138. #define LPI2C_MSR_ALF_SHIFT (11U)
  139. #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
  140. #define LPI2C_MSR_FEF_MASK (0x1000U)
  141. #define LPI2C_MSR_FEF_SHIFT (12U)
  142. #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
  143. #define LPI2C_MSR_PLTF_MASK (0x2000U)
  144. #define LPI2C_MSR_PLTF_SHIFT (13U)
  145. #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
  146. #define LPI2C_MSR_DMF_MASK (0x4000U)
  147. #define LPI2C_MSR_DMF_SHIFT (14U)
  148. #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
  149. #define LPI2C_MSR_MBF_MASK (0x1000000U)
  150. #define LPI2C_MSR_MBF_SHIFT (24U)
  151. #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
  152. #define LPI2C_MSR_BBF_MASK (0x2000000U)
  153. #define LPI2C_MSR_BBF_SHIFT (25U)
  154. #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
  155. /*! @name MIER - Master Interrupt Enable Register */
  156. #define LPI2C_MIER_TDIE_MASK (0x1U)
  157. #define LPI2C_MIER_TDIE_SHIFT (0U)
  158. #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
  159. #define LPI2C_MIER_RDIE_MASK (0x2U)
  160. #define LPI2C_MIER_RDIE_SHIFT (1U)
  161. #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
  162. #define LPI2C_MIER_EPIE_MASK (0x100U)
  163. #define LPI2C_MIER_EPIE_SHIFT (8U)
  164. #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
  165. #define LPI2C_MIER_SDIE_MASK (0x200U)
  166. #define LPI2C_MIER_SDIE_SHIFT (9U)
  167. #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
  168. #define LPI2C_MIER_NDIE_MASK (0x400U)
  169. #define LPI2C_MIER_NDIE_SHIFT (10U)
  170. #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
  171. #define LPI2C_MIER_ALIE_MASK (0x800U)
  172. #define LPI2C_MIER_ALIE_SHIFT (11U)
  173. #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
  174. #define LPI2C_MIER_FEIE_MASK (0x1000U)
  175. #define LPI2C_MIER_FEIE_SHIFT (12U)
  176. #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
  177. #define LPI2C_MIER_PLTIE_MASK (0x2000U)
  178. #define LPI2C_MIER_PLTIE_SHIFT (13U)
  179. #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
  180. #define LPI2C_MIER_DMIE_MASK (0x4000U)
  181. #define LPI2C_MIER_DMIE_SHIFT (14U)
  182. #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
  183. /*! @name MDER - Master DMA Enable Register */
  184. #define LPI2C_MDER_TDDE_MASK (0x1U)
  185. #define LPI2C_MDER_TDDE_SHIFT (0U)
  186. #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
  187. #define LPI2C_MDER_RDDE_MASK (0x2U)
  188. #define LPI2C_MDER_RDDE_SHIFT (1U)
  189. #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
  190. /*! @name MCFGR0 - Master Configuration Register 0 */
  191. #define LPI2C_MCFGR0_HREN_MASK (0x1U)
  192. #define LPI2C_MCFGR0_HREN_SHIFT (0U)
  193. #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
  194. #define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
  195. #define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
  196. #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
  197. #define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
  198. #define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
  199. #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
  200. #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
  201. #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
  202. #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
  203. #define LPI2C_MCFGR0_RDMO_MASK (0x200U)
  204. #define LPI2C_MCFGR0_RDMO_SHIFT (9U)
  205. #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
  206. /*! @name MCFGR1 - Master Configuration Register 1 */
  207. #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
  208. #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
  209. #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
  210. #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
  211. #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
  212. #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
  213. #define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
  214. #define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
  215. #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
  216. #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
  217. #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
  218. #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
  219. #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
  220. #define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
  221. #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
  222. #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
  223. #define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
  224. #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
  225. /*! @name MCFGR2 - Master Configuration Register 2 */
  226. #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
  227. #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
  228. #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
  229. #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
  230. #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
  231. #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
  232. #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
  233. #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
  234. #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
  235. /*! @name MCFGR3 - Master Configuration Register 3 */
  236. #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
  237. #define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
  238. #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
  239. /*! @name MDMR - Master Data Match Register */
  240. #define LPI2C_MDMR_MATCH0_MASK (0xFFU)
  241. #define LPI2C_MDMR_MATCH0_SHIFT (0U)
  242. #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
  243. #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
  244. #define LPI2C_MDMR_MATCH1_SHIFT (16U)
  245. #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
  246. /*! @name MCCR0 - Master Clock Configuration Register 0 */
  247. #define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
  248. #define LPI2C_MCCR0_CLKLO_SHIFT (0U)
  249. #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
  250. #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
  251. #define LPI2C_MCCR0_CLKHI_SHIFT (8U)
  252. #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
  253. #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
  254. #define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
  255. #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
  256. #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
  257. #define LPI2C_MCCR0_DATAVD_SHIFT (24U)
  258. #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
  259. /*! @name MCCR1 - Master Clock Configuration Register 1 */
  260. #define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
  261. #define LPI2C_MCCR1_CLKLO_SHIFT (0U)
  262. #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
  263. #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
  264. #define LPI2C_MCCR1_CLKHI_SHIFT (8U)
  265. #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
  266. #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
  267. #define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
  268. #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
  269. #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
  270. #define LPI2C_MCCR1_DATAVD_SHIFT (24U)
  271. #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
  272. /*! @name MFCR - Master FIFO Control Register */
  273. #define LPI2C_MFCR_TXWATER_MASK (0xFFU)
  274. #define LPI2C_MFCR_TXWATER_SHIFT (0U)
  275. #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
  276. #define LPI2C_MFCR_RXWATER_MASK (0xFF0000U)
  277. #define LPI2C_MFCR_RXWATER_SHIFT (16U)
  278. #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
  279. /*! @name MFSR - Master FIFO Status Register */
  280. #define LPI2C_MFSR_TXCOUNT_MASK (0xFFU)
  281. #define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
  282. #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
  283. #define LPI2C_MFSR_RXCOUNT_MASK (0xFF0000U)
  284. #define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
  285. #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
  286. /*! @name MTDR - Master Transmit Data Register */
  287. #define LPI2C_MTDR_DATA_MASK (0xFFU)
  288. #define LPI2C_MTDR_DATA_SHIFT (0U)
  289. #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
  290. #define LPI2C_MTDR_CMD_MASK (0x700U)
  291. #define LPI2C_MTDR_CMD_SHIFT (8U)
  292. #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
  293. /*! @name MRDR - Master Receive Data Register */
  294. #define LPI2C_MRDR_DATA_MASK (0xFFU)
  295. #define LPI2C_MRDR_DATA_SHIFT (0U)
  296. #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
  297. #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
  298. #define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
  299. #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
  300. /*! @name SCR - Slave Control Register */
  301. #define LPI2C_SCR_SEN_MASK (0x1U)
  302. #define LPI2C_SCR_SEN_SHIFT (0U)
  303. #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
  304. #define LPI2C_SCR_RST_MASK (0x2U)
  305. #define LPI2C_SCR_RST_SHIFT (1U)
  306. #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
  307. #define LPI2C_SCR_FILTEN_MASK (0x10U)
  308. #define LPI2C_SCR_FILTEN_SHIFT (4U)
  309. #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
  310. #define LPI2C_SCR_FILTDZ_MASK (0x20U)
  311. #define LPI2C_SCR_FILTDZ_SHIFT (5U)
  312. #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
  313. #define LPI2C_SCR_RTF_MASK (0x100U)
  314. #define LPI2C_SCR_RTF_SHIFT (8U)
  315. #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
  316. #define LPI2C_SCR_RRF_MASK (0x200U)
  317. #define LPI2C_SCR_RRF_SHIFT (9U)
  318. #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
  319. /*! @name SSR - Slave Status Register */
  320. #define LPI2C_SSR_TDF_MASK (0x1U)
  321. #define LPI2C_SSR_TDF_SHIFT (0U)
  322. #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
  323. #define LPI2C_SSR_RDF_MASK (0x2U)
  324. #define LPI2C_SSR_RDF_SHIFT (1U)
  325. #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
  326. #define LPI2C_SSR_AVF_MASK (0x4U)
  327. #define LPI2C_SSR_AVF_SHIFT (2U)
  328. #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
  329. #define LPI2C_SSR_TAF_MASK (0x8U)
  330. #define LPI2C_SSR_TAF_SHIFT (3U)
  331. #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
  332. #define LPI2C_SSR_RSF_MASK (0x100U)
  333. #define LPI2C_SSR_RSF_SHIFT (8U)
  334. #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
  335. #define LPI2C_SSR_SDF_MASK (0x200U)
  336. #define LPI2C_SSR_SDF_SHIFT (9U)
  337. #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
  338. #define LPI2C_SSR_BEF_MASK (0x400U)
  339. #define LPI2C_SSR_BEF_SHIFT (10U)
  340. #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
  341. #define LPI2C_SSR_FEF_MASK (0x800U)
  342. #define LPI2C_SSR_FEF_SHIFT (11U)
  343. #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
  344. #define LPI2C_SSR_AM0F_MASK (0x1000U)
  345. #define LPI2C_SSR_AM0F_SHIFT (12U)
  346. #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
  347. #define LPI2C_SSR_AM1F_MASK (0x2000U)
  348. #define LPI2C_SSR_AM1F_SHIFT (13U)
  349. #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
  350. #define LPI2C_SSR_GCF_MASK (0x4000U)
  351. #define LPI2C_SSR_GCF_SHIFT (14U)
  352. #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
  353. #define LPI2C_SSR_SARF_MASK (0x8000U)
  354. #define LPI2C_SSR_SARF_SHIFT (15U)
  355. #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
  356. #define LPI2C_SSR_SBF_MASK (0x1000000U)
  357. #define LPI2C_SSR_SBF_SHIFT (24U)
  358. #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
  359. #define LPI2C_SSR_BBF_MASK (0x2000000U)
  360. #define LPI2C_SSR_BBF_SHIFT (25U)
  361. #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
  362. /*! @name SIER - Slave Interrupt Enable Register */
  363. #define LPI2C_SIER_TDIE_MASK (0x1U)
  364. #define LPI2C_SIER_TDIE_SHIFT (0U)
  365. #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
  366. #define LPI2C_SIER_RDIE_MASK (0x2U)
  367. #define LPI2C_SIER_RDIE_SHIFT (1U)
  368. #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
  369. #define LPI2C_SIER_AVIE_MASK (0x4U)
  370. #define LPI2C_SIER_AVIE_SHIFT (2U)
  371. #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
  372. #define LPI2C_SIER_TAIE_MASK (0x8U)
  373. #define LPI2C_SIER_TAIE_SHIFT (3U)
  374. #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
  375. #define LPI2C_SIER_RSIE_MASK (0x100U)
  376. #define LPI2C_SIER_RSIE_SHIFT (8U)
  377. #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
  378. #define LPI2C_SIER_SDIE_MASK (0x200U)
  379. #define LPI2C_SIER_SDIE_SHIFT (9U)
  380. #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
  381. #define LPI2C_SIER_BEIE_MASK (0x400U)
  382. #define LPI2C_SIER_BEIE_SHIFT (10U)
  383. #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
  384. #define LPI2C_SIER_FEIE_MASK (0x800U)
  385. #define LPI2C_SIER_FEIE_SHIFT (11U)
  386. #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
  387. #define LPI2C_SIER_AM0IE_MASK (0x1000U)
  388. #define LPI2C_SIER_AM0IE_SHIFT (12U)
  389. #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
  390. #define LPI2C_SIER_AM1F_MASK (0x2000U)
  391. #define LPI2C_SIER_AM1F_SHIFT (13U)
  392. #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK)
  393. #define LPI2C_SIER_GCIE_MASK (0x4000U)
  394. #define LPI2C_SIER_GCIE_SHIFT (14U)
  395. #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
  396. #define LPI2C_SIER_SARIE_MASK (0x8000U)
  397. #define LPI2C_SIER_SARIE_SHIFT (15U)
  398. #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
  399. /*! @name SDER - Slave DMA Enable Register */
  400. #define LPI2C_SDER_TDDE_MASK (0x1U)
  401. #define LPI2C_SDER_TDDE_SHIFT (0U)
  402. #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
  403. #define LPI2C_SDER_RDDE_MASK (0x2U)
  404. #define LPI2C_SDER_RDDE_SHIFT (1U)
  405. #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
  406. #define LPI2C_SDER_AVDE_MASK (0x4U)
  407. #define LPI2C_SDER_AVDE_SHIFT (2U)
  408. #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
  409. /*! @name SCFGR1 - Slave Configuration Register 1 */
  410. #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
  411. #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
  412. #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
  413. #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
  414. #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
  415. #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
  416. #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
  417. #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
  418. #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
  419. #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
  420. #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
  421. #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
  422. #define LPI2C_SCFGR1_GCEN_MASK (0x100U)
  423. #define LPI2C_SCFGR1_GCEN_SHIFT (8U)
  424. #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
  425. #define LPI2C_SCFGR1_SAEN_MASK (0x200U)
  426. #define LPI2C_SCFGR1_SAEN_SHIFT (9U)
  427. #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
  428. #define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
  429. #define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
  430. #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
  431. #define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
  432. #define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
  433. #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
  434. #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
  435. #define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
  436. #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
  437. #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
  438. #define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
  439. #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
  440. #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
  441. #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
  442. #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
  443. /*! @name SCFGR2 - Slave Configuration Register 2 */
  444. #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
  445. #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
  446. #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
  447. #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
  448. #define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
  449. #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
  450. #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
  451. #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
  452. #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
  453. #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
  454. #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
  455. #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
  456. /*! @name SAMR - Slave Address Match Register */
  457. #define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
  458. #define LPI2C_SAMR_ADDR0_SHIFT (1U)
  459. #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
  460. #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
  461. #define LPI2C_SAMR_ADDR1_SHIFT (17U)
  462. #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
  463. /*! @name SASR - Slave Address Status Register */
  464. #define LPI2C_SASR_RADDR_MASK (0x7FFU)
  465. #define LPI2C_SASR_RADDR_SHIFT (0U)
  466. #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
  467. #define LPI2C_SASR_ANV_MASK (0x4000U)
  468. #define LPI2C_SASR_ANV_SHIFT (14U)
  469. #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
  470. /*! @name STAR - Slave Transmit ACK Register */
  471. #define LPI2C_STAR_TXNACK_MASK (0x1U)
  472. #define LPI2C_STAR_TXNACK_SHIFT (0U)
  473. #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
  474. /*! @name STDR - Slave Transmit Data Register */
  475. #define LPI2C_STDR_DATA_MASK (0xFFU)
  476. #define LPI2C_STDR_DATA_SHIFT (0U)
  477. #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
  478. /*! @name SRDR - Slave Receive Data Register */
  479. #define LPI2C_SRDR_DATA_MASK (0xFFU)
  480. #define LPI2C_SRDR_DATA_SHIFT (0U)
  481. #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
  482. #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
  483. #define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
  484. #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
  485. #define LPI2C_SRDR_SOF_MASK (0x8000U)
  486. #define LPI2C_SRDR_SOF_SHIFT (15U)
  487. #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
  488. #endif /* __ASM_ARCH_IMX_I2C_H__ */