fsl_tgec.h 8.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. */
  6. #ifndef __TGEC_H__
  7. #define __TGEC_H__
  8. #include <phy.h>
  9. struct tgec {
  10. /* 10GEC general control and status registers */
  11. u32 tgec_id; /* Controller ID register */
  12. u32 res0;
  13. u32 command_config; /* Control and configuration register */
  14. u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
  15. u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
  16. u32 maxfrm; /* Maximum frame length register */
  17. u32 pause_quant; /* Pause quanta register */
  18. u32 res1[4];
  19. u32 hashtable_ctrl; /* Hash table control register */
  20. u32 res2[4];
  21. u32 status; /* MAC status register */
  22. u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
  23. u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */
  24. u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */
  25. u32 res3[4];
  26. u32 imask; /* Interrupt mask register */
  27. u32 ievent; /* Interrupt event register */
  28. u32 res4[6];
  29. /* 10GEC statistics counter registers */
  30. u32 tx_frame_u; /* Tx frame counter upper */
  31. u32 tx_frame_l; /* Tx frame counter lower */
  32. u32 rx_frame_u; /* Rx frame counter upper */
  33. u32 rx_frame_l; /* Rx frame counter lower */
  34. u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
  35. u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
  36. u32 rx_align_err_u; /* Rx alignment error upper */
  37. u32 rx_align_err_l; /* Rx alignment error lower */
  38. u32 tx_pause_frame_u; /* Tx valid pause frame upper */
  39. u32 tx_pause_frame_l; /* Tx valid pause frame lower */
  40. u32 rx_pause_frame_u; /* Rx valid pause frame upper */
  41. u32 rx_pause_frame_l; /* Rx valid pause frame upper */
  42. u32 rx_long_err_u; /* Rx too long frame error upper */
  43. u32 rx_long_err_l; /* Rx too long frame error lower */
  44. u32 rx_frame_err_u; /* Rx frame length error upper */
  45. u32 rx_frame_err_l; /* Rx frame length error lower */
  46. u32 tx_vlan_u; /* Tx VLAN frame upper */
  47. u32 tx_vlan_l; /* Tx VLAN frame lower */
  48. u32 rx_vlan_u; /* Rx VLAN frame upper */
  49. u32 rx_vlan_l; /* Rx VLAN frame lower */
  50. u32 tx_oct_u; /* Tx octets upper */
  51. u32 tx_oct_l; /* Tx octets lower */
  52. u32 rx_oct_u; /* Rx octets upper */
  53. u32 rx_oct_l; /* Rx octets lower */
  54. u32 rx_uni_u; /* Rx unicast frame upper */
  55. u32 rx_uni_l; /* Rx unicast frame lower */
  56. u32 rx_multi_u; /* Rx multicast frame upper */
  57. u32 rx_multi_l; /* Rx multicast frame lower */
  58. u32 rx_brd_u; /* Rx broadcast frame upper */
  59. u32 rx_brd_l; /* Rx broadcast frame lower */
  60. u32 tx_frame_err_u; /* Tx frame error upper */
  61. u32 tx_frame_err_l; /* Tx frame error lower */
  62. u32 tx_uni_u; /* Tx unicast frame upper */
  63. u32 tx_uni_l; /* Tx unicast frame lower */
  64. u32 tx_multi_u; /* Tx multicast frame upper */
  65. u32 tx_multi_l; /* Tx multicast frame lower */
  66. u32 tx_brd_u; /* Tx broadcast frame upper */
  67. u32 tx_brd_l; /* Tx broadcast frame lower */
  68. u32 rx_drop_u; /* Rx dropped packets upper */
  69. u32 rx_drop_l; /* Rx dropped packets lower */
  70. u32 rx_eoct_u; /* Rx ethernet octets upper */
  71. u32 rx_eoct_l; /* Rx ethernet octets lower */
  72. u32 rx_pkt_u; /* Rx packets upper */
  73. u32 rx_pkt_l; /* Rx packets lower */
  74. u32 tx_undsz_u; /* Undersized packet upper */
  75. u32 tx_undsz_l; /* Undersized packet lower */
  76. u32 rx_64_u; /* Rx 64 oct packet upper */
  77. u32 rx_64_l; /* Rx 64 oct packet lower */
  78. u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
  79. u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
  80. u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
  81. u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
  82. u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
  83. u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
  84. u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
  85. u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
  86. u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
  87. u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
  88. u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
  89. u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
  90. u32 tx_oversz_u; /* oversized packet upper */
  91. u32 tx_oversz_l; /* oversized packet lower */
  92. u32 tx_jabber_u; /* Jabber packet upper */
  93. u32 tx_jabber_l; /* Jabber packet lower */
  94. u32 tx_frag_u; /* Fragment packet upper */
  95. u32 tx_frag_l; /* Fragment packet lower */
  96. u32 rx_err_u; /* Rx frame error upper */
  97. u32 rx_err_l; /* Rx frame error lower */
  98. u32 res5[0x39a];
  99. };
  100. /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
  101. #define EC10G_ID_VER_MASK 0x0000ff00
  102. #define EC10G_ID_VER_SHIFT 8
  103. #define EC10G_ID_REV_MASK 0x000000ff
  104. /* COMMAND_CONFIG - command and configuration register */
  105. #define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */
  106. #define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */
  107. #define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */
  108. #define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */
  109. #define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */
  110. #define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */
  111. #define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */
  112. #define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */
  113. #define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */
  114. #define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */
  115. #define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */
  116. #define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */
  117. #define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */
  118. #define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */
  119. #define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
  120. #define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
  121. #define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
  122. /* HASHTABLE_CTRL - Hashtable control register */
  123. #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
  124. #define HASHTABLE_CTRL_ADDR_MASK 0x000001ff
  125. /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
  126. #define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff
  127. /* IMASK - interrupt mask register */
  128. #define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */
  129. #define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */
  130. #define IMASK_REM_FAULT 0x00004000 /* remote fault mask */
  131. #define IMASK_LOC_FAULT 0x00002000 /* local fault mask */
  132. #define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
  133. #define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
  134. #define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
  135. #define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
  136. #define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
  137. #define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
  138. #define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
  139. #define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
  140. #define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
  141. #define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
  142. #define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
  143. #define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
  144. #define IMASK_MASK_ALL 0x00000000
  145. /* IEVENT - interrupt event register */
  146. #define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */
  147. #define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */
  148. #define IEVENT_REM_FAULT 0x00004000 /* remote fault */
  149. #define IEVENT_LOC_FAULT 0x00002000 /* local fault */
  150. #define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
  151. #define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
  152. #define IEVENT_TX_ER 0x00000200 /* Tx frame error */
  153. #define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
  154. #define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
  155. #define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
  156. #define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
  157. #define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
  158. #define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
  159. #define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
  160. #define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
  161. #define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
  162. #define IEVENT_CLEAR_ALL 0xffffffff
  163. struct tgec_mdio_controller {
  164. u32 res0[0xc];
  165. u32 mdio_stat; /* MDIO configuration and status */
  166. u32 mdio_ctl; /* MDIO control */
  167. u32 mdio_data; /* MDIO data */
  168. u32 mdio_addr; /* MDIO address */
  169. };
  170. #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
  171. #define MDIO_STAT_BSY (1 << 0)
  172. #define MDIO_STAT_RD_ER (1 << 1)
  173. #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
  174. #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
  175. #define MDIO_CTL_PRE_DIS (1 << 10)
  176. #define MDIO_CTL_SCAN_EN (1 << 11)
  177. #define MDIO_CTL_POST_INC (1 << 14)
  178. #define MDIO_CTL_READ (1 << 15)
  179. #define MDIO_DATA(x) (x & 0xffff)
  180. #define MDIO_DATA_BSY (1 << 31)
  181. struct fsl_enet_mac;
  182. void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
  183. int max_rx_len);
  184. #endif