fsl_sec.h 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Common internal memory map for some Freescale SoCs
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef __FSL_SEC_H
  8. #define __FSL_SEC_H
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #ifdef CONFIG_SYS_FSL_SEC_LE
  12. #define sec_in32(a) in_le32(a)
  13. #define sec_out32(a, v) out_le32(a, v)
  14. #define sec_in16(a) in_le16(a)
  15. #define sec_clrbits32 clrbits_le32
  16. #define sec_setbits32 setbits_le32
  17. #elif defined(CONFIG_SYS_FSL_SEC_BE)
  18. #define sec_in32(a) in_be32(a)
  19. #define sec_out32(a, v) out_be32(a, v)
  20. #define sec_in16(a) in_be16(a)
  21. #define sec_clrbits32 clrbits_be32
  22. #define sec_setbits32 setbits_be32
  23. #elif defined(CONFIG_SYS_FSL_HAS_SEC)
  24. #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
  25. #endif
  26. /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
  27. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  28. /* RNG4 TRNG test registers */
  29. struct rng4tst {
  30. #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
  31. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
  32. both entropy shifter and
  33. statistical checker */
  34. #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
  35. entropy shifter and
  36. statistical checker */
  37. #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
  38. entropy shifter, raw data
  39. in statistical checker */
  40. #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
  41. u32 rtmctl; /* misc. control register */
  42. u32 rtscmisc; /* statistical check misc. register */
  43. u32 rtpkrrng; /* poker range register */
  44. #define RTSDCTL_ENT_DLY_MIN 3200
  45. #define RTSDCTL_ENT_DLY_MAX 12800
  46. union {
  47. u32 rtpkrmax; /* PRGM=1: poker max. limit register */
  48. u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
  49. };
  50. #define RTSDCTL_ENT_DLY_SHIFT 16
  51. #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
  52. u32 rtsdctl; /* seed control register */
  53. union {
  54. u32 rtsblim; /* PRGM=1: sparse bit limit register */
  55. u32 rttotsam; /* PRGM=0: total samples register */
  56. };
  57. u32 rtfreqmin; /* frequency count min. limit register */
  58. #define RTFRQMAX_DISABLE (1 << 20)
  59. union {
  60. u32 rtfreqmax; /* PRGM=1: freq. count max. limit register */
  61. u32 rtfreqcnt; /* PRGM=0: freq. count register */
  62. };
  63. u32 rsvd1[40];
  64. #define RDSTA_IF(idx) (0x00000001 << (idx))
  65. #define RDSTA_PR(idx) (0x00000010 << (idx))
  66. #define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0))
  67. #define RDSTA_SKVN 0x40000000
  68. u32 rdsta; /*RNG DRNG Status Register*/
  69. u32 rsvd2[15];
  70. };
  71. /* Version registers (Era 10+) */
  72. struct version_regs {
  73. u32 crca; /* CRCA_VERSION */
  74. u32 afha; /* AFHA_VERSION */
  75. u32 kfha; /* KFHA_VERSION */
  76. u32 pkha; /* PKHA_VERSION */
  77. u32 aesa; /* AESA_VERSION */
  78. u32 mdha; /* MDHA_VERSION */
  79. u32 desa; /* DESA_VERSION */
  80. u32 snw8a; /* SNW8A_VERSION */
  81. u32 snw9a; /* SNW9A_VERSION */
  82. u32 zuce; /* ZUCE_VERSION */
  83. u32 zuca; /* ZUCA_VERSION */
  84. u32 ccha; /* CCHA_VERSION */
  85. u32 ptha; /* PTHA_VERSION */
  86. u32 rng; /* RNG_VERSION */
  87. u32 trng; /* TRNG_VERSION */
  88. u32 aaha; /* AAHA_VERSION */
  89. u32 rsvd[10];
  90. u32 sr; /* SR_VERSION */
  91. u32 dma; /* DMA_VERSION */
  92. u32 ai; /* AI_VERSION */
  93. u32 qi; /* QI_VERSION */
  94. u32 jr; /* JR_VERSION */
  95. u32 deco; /* DECO_VERSION */
  96. };
  97. #define CHA_VER_NUM_MASK 0x000000ff
  98. #define CHA_VER_MISC_SHIFT 8
  99. #define CHA_VER_MISC_MASK 0x0000ff00
  100. #define CHA_VER_REV_SHIFT 16
  101. #define CHA_VER_REV_MASK 0x00ff0000
  102. #define CHA_VER_VID_SHIFT 24
  103. #define CHA_VER_VID_MASK 0xff000000
  104. typedef struct ccsr_sec {
  105. u32 res0;
  106. u32 mcfgr; /* Master CFG Register */
  107. u8 res1[0x4];
  108. u32 scfgr;
  109. struct {
  110. u32 ms; /* Job Ring LIODN Register, MS */
  111. u32 ls; /* Job Ring LIODN Register, LS */
  112. } jrliodnr[4];
  113. u8 res2[0x2c];
  114. u32 jrstartr; /* Job Ring Start Register */
  115. struct {
  116. u32 ms; /* RTIC LIODN Register, MS */
  117. u32 ls; /* RTIC LIODN Register, LS */
  118. } rticliodnr[4];
  119. u8 res3[0x1c];
  120. u32 decorr; /* DECO Request Register */
  121. struct {
  122. u32 ms; /* DECO LIODN Register, MS */
  123. u32 ls; /* DECO LIODN Register, LS */
  124. } decoliodnr[16];
  125. u32 dar; /* DECO Avail Register */
  126. u32 drr; /* DECO Reset Register */
  127. u8 res5[0x4d8];
  128. struct rng4tst rng; /* RNG Registers */
  129. u8 res6[0x780];
  130. struct version_regs vreg; /* version registers since era 10 */
  131. u8 res7[0xa0];
  132. u32 crnr_ms; /* CHA Revision Number Register, MS */
  133. u32 crnr_ls; /* CHA Revision Number Register, LS */
  134. u32 ctpr_ms; /* Compile Time Parameters Register, MS */
  135. u32 ctpr_ls; /* Compile Time Parameters Register, LS */
  136. u8 res8[0x10];
  137. u32 far_ms; /* Fault Address Register, MS */
  138. u32 far_ls; /* Fault Address Register, LS */
  139. u32 falr; /* Fault Address LIODN Register */
  140. u32 fadr; /* Fault Address Detail Register */
  141. u8 res9[0x4];
  142. u32 csta; /* CAAM Status Register */
  143. u32 smpart; /* Secure Memory Partition Parameters */
  144. u32 smvid; /* Secure Memory Version ID */
  145. u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
  146. u32 ccbvid; /* CHA Cluster Block Version ID Register */
  147. u32 chavid_ms; /* CHA Version ID Register, MS */
  148. u32 chavid_ls; /* CHA Version ID Register, LS */
  149. u32 chanum_ms; /* CHA Number Register, MS */
  150. u32 chanum_ls; /* CHA Number Register, LS */
  151. u32 secvid_ms; /* SEC Version ID Register, MS */
  152. u32 secvid_ls; /* SEC Version ID Register, LS */
  153. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  154. u8 res10[0x6f020];
  155. #else
  156. u8 res10[0x6020];
  157. #endif
  158. u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
  159. u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
  160. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
  161. u8 res11[0x8ffd8];
  162. #else
  163. u8 res11[0x8fd8];
  164. #endif
  165. } ccsr_sec_t;
  166. #define SEC_CTPR_MS_AXI_LIODN 0x08000000
  167. #define SEC_CTPR_MS_QI 0x02000000
  168. #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
  169. #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
  170. #define SEC_RVID_MA 0x0f000000
  171. #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
  172. #define SEC_CHANUM_MS_JRNUM_SHIFT 28
  173. #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
  174. #define SEC_CHANUM_MS_DECONUM_SHIFT 24
  175. #define SEC_SECVID_MS_IPID_MASK 0xffff0000
  176. #define SEC_SECVID_MS_IPID_SHIFT 16
  177. #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
  178. #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
  179. #define SEC_CCBVID_ERA_MASK 0xff000000
  180. #define SEC_CCBVID_ERA_SHIFT 24
  181. #define SEC_SCFGR_RDBENABLE 0x00000400
  182. #define SEC_SCFGR_VIRT_EN 0x00008000
  183. #define SEC_CHAVID_LS_RNG_SHIFT 16
  184. #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
  185. #define CONFIG_JRSTARTR_JR0 0x00000001
  186. struct jr_regs {
  187. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  188. !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
  189. u32 irba_l;
  190. u32 irba_h;
  191. #else
  192. u32 irba_h;
  193. u32 irba_l;
  194. #endif
  195. u32 rsvd1;
  196. u32 irs;
  197. u32 rsvd2;
  198. u32 irsa;
  199. u32 rsvd3;
  200. u32 irja;
  201. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  202. !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
  203. u32 orba_l;
  204. u32 orba_h;
  205. #else
  206. u32 orba_h;
  207. u32 orba_l;
  208. #endif
  209. u32 rsvd4;
  210. u32 ors;
  211. u32 rsvd5;
  212. u32 orjr;
  213. u32 rsvd6;
  214. u32 orsf;
  215. u32 rsvd7;
  216. u32 jrsta;
  217. u32 rsvd8;
  218. u32 jrint;
  219. u32 jrcfg0;
  220. u32 jrcfg1;
  221. u32 rsvd9;
  222. u32 irri;
  223. u32 rsvd10;
  224. u32 orwi;
  225. u32 rsvd11;
  226. u32 jrcr;
  227. };
  228. /*
  229. * Scatter Gather Entry - Specifies the the Scatter Gather Format
  230. * related information
  231. */
  232. struct sg_entry {
  233. #if defined(CONFIG_SYS_FSL_SEC_LE) && \
  234. !(defined(CONFIG_MX6) || defined(CONFIG_MX7))
  235. uint32_t addr_lo; /* Memory Address - lo */
  236. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  237. #else
  238. uint32_t addr_hi; /* Memory Address of start of buffer - hi */
  239. uint32_t addr_lo; /* Memory Address - lo */
  240. #endif
  241. uint32_t len_flag; /* Length of the data in the frame */
  242. #define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
  243. #define SG_ENTRY_EXTENSION_BIT 0x80000000
  244. #define SG_ENTRY_FINAL_BIT 0x40000000
  245. uint32_t bpid_offset;
  246. #define SG_ENTRY_BPID_MASK 0x00FF0000
  247. #define SG_ENTRY_BPID_SHIFT 16
  248. #define SG_ENTRY_OFFSET_MASK 0x00001FFF
  249. #define SG_ENTRY_OFFSET_SHIFT 0
  250. };
  251. #define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
  252. #if defined(CONFIG_MX6) || defined(CONFIG_MX7)
  253. /* Job Ring Base Address */
  254. #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
  255. /* Secure Memory Offset varies accross versions */
  256. #define SM_V1_OFFSET 0x0f4
  257. #define SM_V2_OFFSET 0xa00
  258. /*Secure Memory Versioning */
  259. #define SMVID_V2 0x20105
  260. #define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2)
  261. #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET)
  262. /* CAAM Job Ring 0 Registers */
  263. /* Secure Memory Partition Owner register */
  264. #define SMCSJR_PO (3 << 6)
  265. /* JR Allocation Error */
  266. #define SMCSJR_AERR (3 << 12)
  267. /* Secure memory partition 0 page 0 owner register */
  268. #define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC)
  269. /* Secure memory command register */
  270. #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v))
  271. /* Secure memory command status register */
  272. #define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v))
  273. /* Secure memory access permissions register */
  274. #define CAAM_SMAPJR(v, jr, y) \
  275. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16)
  276. /* Secure memory access group 2 register */
  277. #define CAAM_SMAG2JR(v, jr, y) \
  278. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16)
  279. /* Secure memory access group 1 register */
  280. #define CAAM_SMAG1JR(v, jr, y) \
  281. (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16)
  282. /* Commands and macros for secure memory */
  283. #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4)
  284. #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC)
  285. #define SM_PERM(v) (v == 1 ? 0x10 : 0x4)
  286. #define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8)
  287. #define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC)
  288. #define CMD_PAGE_ALLOC 0x1
  289. #define CMD_PAGE_DEALLOC 0x2
  290. #define CMD_PART_DEALLOC 0x3
  291. #define CMD_INQUIRY 0x5
  292. #define CMD_COMPLETE (3 << 14)
  293. #define PAGE_AVAILABLE 0
  294. #define PAGE_OWNED (3 << 6)
  295. #define PAGE(x) (x << 16)
  296. #define PARTITION(x) (x << 8)
  297. #define PARTITION_OWNER(x) (0x3 << (x*2))
  298. /* Address of secure 4kbyte pages */
  299. #define SEC_MEM_PAGE0 CAAM_ARB_BASE_ADDR
  300. #define SEC_MEM_PAGE1 (CAAM_ARB_BASE_ADDR + 0x1000)
  301. #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000)
  302. #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000)
  303. #define JR_MID 2 /* Matches ROM configuration */
  304. #define KS_G1 (1 << JR_MID) /* CAAM only */
  305. #define PERM 0x0000B008 /* Clear on release, lock SMAP
  306. * lock SMAG group 1 Blob */
  307. /* HAB WRAPPED KEY header */
  308. #define WRP_HDR_SIZE 0x08
  309. #define HDR_TAG 0x81
  310. #define HDR_PAR 0x41
  311. /* HAB WRAPPED KEY Data */
  312. #define HAB_MOD 0x66
  313. #define HAB_ALG 0x55
  314. #define HAB_FLG 0x00
  315. /* Partition and Page IDs */
  316. #define PARTITION_1 1
  317. #define PAGE_1 1
  318. #define ERROR_IN_PAGE_ALLOC 1
  319. #define ECONSTRJDESC -1
  320. #endif
  321. /* blob_dek:
  322. * Encapsulates the src in a secure blob and stores it dst
  323. * @src: reference to the plaintext
  324. * @dst: reference to the output adrress
  325. * @len: size in bytes of src
  326. * @return: 0 on success, error otherwise
  327. */
  328. int blob_dek(const u8 *src, u8 *dst, u8 len);
  329. #if defined(CONFIG_ARCH_C29X)
  330. int sec_init_idx(uint8_t);
  331. #endif
  332. int sec_init(void);
  333. u8 caam_get_era(void);
  334. #endif
  335. #endif /* __FSL_SEC_H */