fsl_pmic.h 3.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #ifndef __FSL_PMIC_H__
  9. #define __FSL_PMIC_H__
  10. /*
  11. * The registers of different PMIC has the same meaning
  12. * but the bit positions of the fields can differ or
  13. * some fields has a meaning only on some devices.
  14. * You have to check with the internal SPI bitmap
  15. * (see Freescale Documentation) to set the registers
  16. * for the device you are using
  17. */
  18. enum {
  19. REG_INT_STATUS0 = 0,
  20. REG_INT_MASK0,
  21. REG_INT_SENSE0,
  22. REG_INT_STATUS1,
  23. REG_INT_MASK1,
  24. REG_INT_SENSE1,
  25. REG_PU_MODE_S,
  26. REG_IDENTIFICATION,
  27. REG_UNUSED0,
  28. REG_ACC0,
  29. REG_ACC1, /*10 */
  30. REG_UNUSED1,
  31. REG_UNUSED2,
  32. REG_POWER_CTL0,
  33. REG_POWER_CTL1,
  34. REG_POWER_CTL2,
  35. REG_REGEN_ASSIGN,
  36. REG_UNUSED3,
  37. REG_MEM_A,
  38. REG_MEM_B,
  39. REG_RTC_TIME, /*20 */
  40. REG_RTC_ALARM,
  41. REG_RTC_DAY,
  42. REG_RTC_DAY_ALARM,
  43. REG_SW_0,
  44. REG_SW_1,
  45. REG_SW_2,
  46. REG_SW_3,
  47. REG_SW_4,
  48. REG_SW_5,
  49. REG_SETTING_0, /*30 */
  50. REG_SETTING_1,
  51. REG_MODE_0,
  52. REG_MODE_1,
  53. REG_POWER_MISC,
  54. REG_UNUSED4,
  55. REG_UNUSED5,
  56. REG_UNUSED6,
  57. REG_UNUSED7,
  58. REG_UNUSED8,
  59. REG_UNUSED9, /*40 */
  60. REG_UNUSED10,
  61. REG_UNUSED11,
  62. REG_ADC0,
  63. REG_ADC1,
  64. REG_ADC2,
  65. REG_ADC3,
  66. REG_ADC4,
  67. REG_CHARGE,
  68. REG_USB0,
  69. REG_USB1, /*50 */
  70. REG_LED_CTL0,
  71. REG_LED_CTL1,
  72. REG_LED_CTL2,
  73. REG_LED_CTL3,
  74. REG_UNUSED12,
  75. REG_UNUSED13,
  76. REG_TRIM0,
  77. REG_TRIM1,
  78. REG_TEST0,
  79. REG_TEST1, /*60 */
  80. REG_TEST2,
  81. REG_TEST3,
  82. REG_TEST4,
  83. PMIC_NUM_OF_REGS,
  84. };
  85. /* REG_POWER_MISC */
  86. #define GPO1EN (1 << 6)
  87. #define GPO1STBY (1 << 7)
  88. #define GPO2EN (1 << 8)
  89. #define GPO2STBY (1 << 9)
  90. #define GPO3EN (1 << 10)
  91. #define GPO3STBY (1 << 11)
  92. #define GPO4EN (1 << 12)
  93. #define GPO4STBY (1 << 13)
  94. #define PWGT1SPIEN (1 << 15)
  95. #define PWGT2SPIEN (1 << 16)
  96. #define PWUP (1 << 21)
  97. /* Power Control 0 */
  98. #define COINCHEN (1 << 23)
  99. #define BATTDETEN (1 << 19)
  100. /* Interrupt status 1 */
  101. #define RTCRSTI (1 << 7)
  102. /* MC34708 Definitions */
  103. #define SWx_VOLT_MASK_MC34708 0x3F
  104. #define SWx_1_110V_MC34708 0x24
  105. #define SWx_1_250V_MC34708 0x30
  106. #define SWx_1_300V_MC34708 0x34
  107. #define TIMER_MASK_MC34708 0x300
  108. #define TIMER_4S_MC34708 0x100
  109. #define VUSBSEL_MC34708 (1 << 2)
  110. #define VUSBEN_MC34708 (1 << 3)
  111. #define SWBST_CTRL 31
  112. #define SWBST_AUTO 0x8
  113. #define MC34708_REG_SW12_OPMODE 28
  114. #define MC34708_SW1AMODE_MASK 0x00000f
  115. #define MC34708_SW1AMHMODE 0x000010
  116. #define MC34708_SW1AUOMODE 0x000020
  117. #define MC34708_SW1DVSSPEED 0x0000c0
  118. #define MC34708_SW2MODE_MASK 0x03c000
  119. #define MC34708_SW2MHMODE 0x040000
  120. #define MC34708_SW2UOMODE 0x080000
  121. #define MC34708_SW2DVSSPEED 0x300000
  122. #define MC34708_PLLEN 0x400000
  123. #define MC34708_PLLX 0x800000
  124. #define MC34708_REG_SW345_OPMODE 29
  125. #define MC34708_SW3MODE_MASK 0x00000f
  126. #define MC34708_SW3MHMODE 0x000010
  127. #define MC34708_SW3UOMODE 0x000020
  128. #define MC34708_SW4AMODE_MASK 0x0003c0
  129. #define MC34708_SW4AMHMODE 0x000400
  130. #define MC34708_SW4AUOMODE 0x000800
  131. #define MC34708_SW4BMODE_MASK 0x00f000
  132. #define MC34708_SW4BMHMODE 0x010000
  133. #define MC34708_SW4BUOMODE 0x020000
  134. #define MC34708_SW5MODE_MASK 0x3c0000
  135. #define MC34708_SW5MHMODE 0x400000
  136. #define MC34708_SW5UOMODE 0x800000
  137. #define SW_MODE_OFFOFF 0x00
  138. #define SW_MODE_PWMOFF 0x01
  139. #define SW_MODE_PFMOFF 0x03
  140. #define SW_MODE_APSOFF 0x04
  141. #define SW_MODE_PWMPWM 0x05
  142. #define SW_MODE_PWMAPS 0x06
  143. #define SW_MODE_APSAPS 0x08
  144. #define SW_MODE_APSPFM 0x0c
  145. #define SW_MODE_PWMPFM 0x0d
  146. #define SW_MODE_PFMPFM 0x0f
  147. #define MC34708_TRANSFER_SIZE 3
  148. #endif