fsl_esdhc.h 7.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * FSL SD/MMC Defines
  4. *-------------------------------------------------------------------
  5. *
  6. * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
  7. * Copyright 2020 NXP
  8. */
  9. #ifndef __FSL_ESDHC_H__
  10. #define __FSL_ESDHC_H__
  11. #include <linux/errno.h>
  12. #include <asm/byteorder.h>
  13. /* needed for the mmc_cfg definition */
  14. #include <mmc.h>
  15. /* FSL eSDHC-specific constants */
  16. #define SYSCTL 0x0002e02c
  17. #define SYSCTL_INITA 0x08000000
  18. #define SYSCTL_TIMEOUT_MASK 0x000f0000
  19. #define SYSCTL_CLOCK_MASK 0x0000fff0
  20. #define SYSCTL_CKEN 0x00000008
  21. #define SYSCTL_PEREN 0x00000004
  22. #define SYSCTL_HCKEN 0x00000002
  23. #define SYSCTL_IPGEN 0x00000001
  24. #define SYSCTL_RSTA 0x01000000
  25. #define SYSCTL_RSTC 0x02000000
  26. #define SYSCTL_RSTD 0x04000000
  27. #define IRQSTAT 0x0002e030
  28. #define IRQSTAT_DMAE (0x10000000)
  29. #define IRQSTAT_AC12E (0x01000000)
  30. #define IRQSTAT_DEBE (0x00400000)
  31. #define IRQSTAT_DCE (0x00200000)
  32. #define IRQSTAT_DTOE (0x00100000)
  33. #define IRQSTAT_CIE (0x00080000)
  34. #define IRQSTAT_CEBE (0x00040000)
  35. #define IRQSTAT_CCE (0x00020000)
  36. #define IRQSTAT_CTOE (0x00010000)
  37. #define IRQSTAT_CINT (0x00000100)
  38. #define IRQSTAT_CRM (0x00000080)
  39. #define IRQSTAT_CINS (0x00000040)
  40. #define IRQSTAT_BRR (0x00000020)
  41. #define IRQSTAT_BWR (0x00000010)
  42. #define IRQSTAT_DINT (0x00000008)
  43. #define IRQSTAT_BGE (0x00000004)
  44. #define IRQSTAT_TC (0x00000002)
  45. #define IRQSTAT_CC (0x00000001)
  46. #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
  47. #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
  48. IRQSTAT_DMAE)
  49. #define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
  50. #define IRQSTATEN 0x0002e034
  51. #define IRQSTATEN_DMAE (0x10000000)
  52. #define IRQSTATEN_AC12E (0x01000000)
  53. #define IRQSTATEN_DEBE (0x00400000)
  54. #define IRQSTATEN_DCE (0x00200000)
  55. #define IRQSTATEN_DTOE (0x00100000)
  56. #define IRQSTATEN_CIE (0x00080000)
  57. #define IRQSTATEN_CEBE (0x00040000)
  58. #define IRQSTATEN_CCE (0x00020000)
  59. #define IRQSTATEN_CTOE (0x00010000)
  60. #define IRQSTATEN_CINT (0x00000100)
  61. #define IRQSTATEN_CRM (0x00000080)
  62. #define IRQSTATEN_CINS (0x00000040)
  63. #define IRQSTATEN_BRR (0x00000020)
  64. #define IRQSTATEN_BWR (0x00000010)
  65. #define IRQSTATEN_DINT (0x00000008)
  66. #define IRQSTATEN_BGE (0x00000004)
  67. #define IRQSTATEN_TC (0x00000002)
  68. #define IRQSTATEN_CC (0x00000001)
  69. /* eSDHC control register */
  70. #define ESDHCCTL 0x0002e40c
  71. #define ESDHCCTL_PCS (0x00080000)
  72. #define ESDHCCTL_FAF (0x00040000)
  73. #define PRSSTAT 0x0002e024
  74. #define PRSSTAT_DAT0 (0x01000000)
  75. #define PRSSTAT_CLSL (0x00800000)
  76. #define PRSSTAT_WPSPL (0x00080000)
  77. #define PRSSTAT_CDPL (0x00040000)
  78. #define PRSSTAT_CINS (0x00010000)
  79. #define PRSSTAT_BREN (0x00000800)
  80. #define PRSSTAT_BWEN (0x00000400)
  81. #define PRSSTAT_SDSTB (0X00000008)
  82. #define PRSSTAT_DLA (0x00000004)
  83. #define PRSSTAT_CICHB (0x00000002)
  84. #define PRSSTAT_CIDHB (0x00000001)
  85. #define PROCTL 0x0002e028
  86. #define PROCTL_INIT 0x00000020
  87. #define PROCTL_DTW_4 0x00000002
  88. #define PROCTL_DTW_8 0x00000004
  89. #define PROCTL_D3CD 0x00000008
  90. #define PROCTL_DMAS_MASK 0x00000300
  91. #define PROCTL_DMAS_SDMA 0x00000000
  92. #define PROCTL_DMAS_ADMA1 0x00000100
  93. #define PROCTL_DMAS_ADMA2 0x00000300
  94. #define PROCTL_VOLT_SEL 0x00000400
  95. #define CMDARG 0x0002e008
  96. #define XFERTYP 0x0002e00c
  97. #define XFERTYP_CMD(x) ((x & 0x3f) << 24)
  98. #define XFERTYP_CMDTYP_NORMAL 0x0
  99. #define XFERTYP_CMDTYP_SUSPEND 0x00400000
  100. #define XFERTYP_CMDTYP_RESUME 0x00800000
  101. #define XFERTYP_CMDTYP_ABORT 0x00c00000
  102. #define XFERTYP_DPSEL 0x00200000
  103. #define XFERTYP_CICEN 0x00100000
  104. #define XFERTYP_CCCEN 0x00080000
  105. #define XFERTYP_RSPTYP_NONE 0
  106. #define XFERTYP_RSPTYP_136 0x00010000
  107. #define XFERTYP_RSPTYP_48 0x00020000
  108. #define XFERTYP_RSPTYP_48_BUSY 0x00030000
  109. #define XFERTYP_MSBSEL 0x00000020
  110. #define XFERTYP_DTDSEL 0x00000010
  111. #define XFERTYP_DDREN 0x00000008
  112. #define XFERTYP_AC12EN 0x00000004
  113. #define XFERTYP_BCEN 0x00000002
  114. #define XFERTYP_DMAEN 0x00000001
  115. #define CINS_TIMEOUT 1000
  116. #define PIO_TIMEOUT 500
  117. #define DSADDR 0x2e004
  118. #define CMDRSP0 0x2e010
  119. #define CMDRSP1 0x2e014
  120. #define CMDRSP2 0x2e018
  121. #define CMDRSP3 0x2e01c
  122. #define DATPORT 0x2e020
  123. #define WML 0x2e044
  124. #define WML_WRITE 0x00010000
  125. #ifdef CONFIG_FSL_SDHC_V2_3
  126. #define WML_RD_WML_MAX 0x80
  127. #define WML_WR_WML_MAX 0x80
  128. #define WML_RD_WML_MAX_VAL 0x0
  129. #define WML_WR_WML_MAX_VAL 0x0
  130. #define WML_RD_WML_MASK 0x7f
  131. #define WML_WR_WML_MASK 0x7f0000
  132. #else
  133. #define WML_RD_WML_MAX 0x10
  134. #define WML_WR_WML_MAX 0x80
  135. #define WML_RD_WML_MAX_VAL 0x10
  136. #define WML_WR_WML_MAX_VAL 0x80
  137. #define WML_RD_WML_MASK 0xff
  138. #define WML_WR_WML_MASK 0xff0000
  139. #endif
  140. #define BLKATTR 0x2e004
  141. #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
  142. #define BLKATTR_SIZE(x) (x & 0x1fff)
  143. #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
  144. /* Auto CMD error status register / system control 2 register */
  145. #define EXECUTE_TUNING 0x00400000
  146. #define SMPCLKSEL 0x00800000
  147. #define UHSM_MASK 0x00070000
  148. #define UHSM_SDR104_HS200 0x00030000
  149. /* Host controller capabilities register */
  150. #define HOSTCAPBLT_VS18 0x04000000
  151. #define HOSTCAPBLT_VS30 0x02000000
  152. #define HOSTCAPBLT_VS33 0x01000000
  153. #define HOSTCAPBLT_SRS 0x00800000
  154. #define HOSTCAPBLT_DMAS 0x00400000
  155. #define HOSTCAPBLT_HSS 0x00200000
  156. /* Tuning block control register */
  157. #define TBCTL_TB_EN 0x00000004
  158. #define HS400_MODE 0x00000010
  159. #define HS400_WNDW_ADJUST 0x00000040
  160. /* SD clock control register */
  161. #define CMD_CLK_CTL 0x00008000
  162. /* SD timing control register */
  163. #define FLW_CTL_BG 0x00008000
  164. /* DLL config 0 register */
  165. #define DLL_ENABLE 0x80000000
  166. #define DLL_RESET 0x40000000
  167. #define DLL_FREQ_SEL 0x08000000
  168. /* DLL status 0 register */
  169. #define DLL_STS_SLV_LOCK 0x08000000
  170. #define MAX_TUNING_LOOP 40
  171. #define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff)
  172. #define VENDOR_V_10 0x00
  173. #define VENDOR_V_20 0x10
  174. #define VENDOR_V_21 0x11
  175. #define VENDOR_V_22 0x12
  176. #define VENDOR_V_23 0x13
  177. #define VENDOR_V_30 0x20
  178. #define VENDOR_V_31 0x21
  179. #define VENDOR_V_32 0x22
  180. struct fsl_esdhc_cfg {
  181. phys_addr_t esdhc_base;
  182. u32 sdhc_clk;
  183. u8 max_bus_width;
  184. int vs18_enable; /* Use 1.8V if set to 1 */
  185. struct mmc_config cfg;
  186. };
  187. /* Select the correct accessors depending on endianess */
  188. #if defined CONFIG_SYS_FSL_ESDHC_LE
  189. #define esdhc_read32 in_le32
  190. #define esdhc_write32 out_le32
  191. #define esdhc_clrsetbits32 clrsetbits_le32
  192. #define esdhc_clrbits32 clrbits_le32
  193. #define esdhc_setbits32 setbits_le32
  194. #elif defined(CONFIG_SYS_FSL_ESDHC_BE)
  195. #define esdhc_read32 in_be32
  196. #define esdhc_write32 out_be32
  197. #define esdhc_clrsetbits32 clrsetbits_be32
  198. #define esdhc_clrbits32 clrbits_be32
  199. #define esdhc_setbits32 setbits_be32
  200. #elif __BYTE_ORDER == __LITTLE_ENDIAN
  201. #define esdhc_read32 in_le32
  202. #define esdhc_write32 out_le32
  203. #define esdhc_clrsetbits32 clrsetbits_le32
  204. #define esdhc_clrbits32 clrbits_le32
  205. #define esdhc_setbits32 setbits_le32
  206. #elif __BYTE_ORDER == __BIG_ENDIAN
  207. #define esdhc_read32 in_be32
  208. #define esdhc_write32 out_be32
  209. #define esdhc_clrsetbits32 clrsetbits_be32
  210. #define esdhc_clrbits32 clrbits_be32
  211. #define esdhc_setbits32 setbits_be32
  212. #else
  213. #error "Endianess is not defined: please fix to continue"
  214. #endif
  215. #ifdef CONFIG_FSL_ESDHC
  216. int fsl_esdhc_mmc_init(struct bd_info *bis);
  217. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
  218. void fdt_fixup_esdhc(void *blob, struct bd_info *bd);
  219. #else
  220. static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; }
  221. static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {}
  222. #endif /* CONFIG_FSL_ESDHC */
  223. void __noreturn mmc_boot(void);
  224. void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
  225. #endif /* __FSL_ESDHC_H__ */