fsl_dtsec.h 9.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __DTSEC_H__
  6. #define __DTSEC_H__
  7. #include <asm/types.h>
  8. struct dtsec {
  9. u32 tsec_id; /* controller ID and version */
  10. u32 tsec_id2; /* controller ID and configuration */
  11. u32 ievent; /* interrupt event */
  12. u32 imask; /* interrupt mask */
  13. u32 res0;
  14. u32 ecntrl; /* ethernet control and configuration */
  15. u32 ptv; /* pause time value */
  16. u32 tbipa; /* TBI PHY address */
  17. u32 res1[8];
  18. u32 tctrl; /* Transmit control register */
  19. u32 res2[3];
  20. u32 rctrl; /* Receive control register */
  21. u32 res3[11];
  22. u32 igaddr[8]; /* Individual group address */
  23. u32 gaddr[8]; /* group address */
  24. u32 res4[16];
  25. u32 maccfg1; /* MAC configuration register 1 */
  26. u32 maccfg2; /* MAC configuration register 2 */
  27. u32 ipgifg; /* inter-packet/inter-frame gap */
  28. u32 hafdup; /* half-duplex control */
  29. u32 maxfrm; /* Maximum frame size */
  30. u32 res5[3];
  31. u32 miimcfg; /* MII management configuration */
  32. u32 miimcom; /* MII management command */
  33. u32 miimadd; /* MII management address */
  34. u32 miimcon; /* MII management control */
  35. u32 miimstat; /* MII management status */
  36. u32 miimind; /* MII management indicator */
  37. u32 res6;
  38. u32 ifstat; /* Interface status */
  39. u32 macstnaddr1; /* MAC station address 1 */
  40. u32 macstnaddr2; /* MAC station address 2 */
  41. u32 res7[46];
  42. /* transmit and receive counter */
  43. u32 tr64; /* Tx and Rx 64 bytes frame */
  44. u32 tr127; /* Tx and Rx 65 to 127 bytes frame */
  45. u32 tr255; /* Tx and Rx 128 to 255 bytes frame */
  46. u32 tr511; /* Tx and Rx 256 to 511 bytes frame */
  47. u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */
  48. u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */
  49. u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */
  50. /* receive counters */
  51. u32 rbyt; /* Receive byte counter */
  52. u32 rpkt; /* Receive packet counter */
  53. u32 rfcs; /* Receive FCS error */
  54. u32 rmca; /* Receive multicast packet */
  55. u32 rbca; /* Receive broadcast packet */
  56. u32 rxcf; /* Receive control frame */
  57. u32 rxpf; /* Receive pause frame */
  58. u32 rxuo; /* Receive unknown OP code */
  59. u32 raln; /* Receive alignment error */
  60. u32 rflr; /* Receive frame length error */
  61. u32 rcde; /* Receive code error */
  62. u32 rcse; /* Receive carrier sense error */
  63. u32 rund; /* Receive undersize packet */
  64. u32 rovr; /* Receive oversize packet */
  65. u32 rfrg; /* Receive fragments counter */
  66. u32 rjbr; /* Receive jabber counter */
  67. u32 rdrp; /* Receive drop counter */
  68. /* transmit counters */
  69. u32 tbyt; /* Transmit byte counter */
  70. u32 tpkt; /* Transmit packet */
  71. u32 tmca; /* Transmit multicast packet */
  72. u32 tbca; /* Transmit broadcast packet */
  73. u32 txpf; /* Transmit pause control frame */
  74. u32 tdfr; /* Transmit deferral packet */
  75. u32 tedf; /* Transmit excessive deferral pkt */
  76. u32 tscl; /* Transmit single collision pkt */
  77. u32 tmcl; /* Transmit multiple collision pkt */
  78. u32 tlcl; /* Transmit late collision pkt */
  79. u32 txcl; /* Transmit excessive collision */
  80. u32 tncl; /* Transmit total collision */
  81. u32 res8;
  82. u32 tdrp; /* Transmit drop frame */
  83. u32 tjbr; /* Transmit jabber frame */
  84. u32 tfcs; /* Transmit FCS error */
  85. u32 txcf; /* Transmit control frame */
  86. u32 tovr; /* Transmit oversize frame */
  87. u32 tund; /* Transmit undersize frame */
  88. u32 tfrg; /* Transmit fragments frame */
  89. /* counter controls */
  90. u32 car1; /* carry register 1 */
  91. u32 car2; /* carry register 2 */
  92. u32 cam1; /* carry register 1 mask */
  93. u32 cam2; /* carry register 2 mask */
  94. u32 res9[80];
  95. };
  96. /* TBI register addresses */
  97. #define TBI_CR 0x00
  98. #define TBI_SR 0x01
  99. #define TBI_ANA 0x04
  100. #define TBI_ANLPBPA 0x05
  101. #define TBI_ANEX 0x06
  102. #define TBI_TBICON 0x11
  103. /* TBI MDIO register bit fields*/
  104. #define TBICON_CLK_SELECT 0x0020
  105. #define TBIANA_ASYMMETRIC_PAUSE 0x0100
  106. #define TBIANA_SYMMETRIC_PAUSE 0x0080
  107. #define TBIANA_HALF_DUPLEX 0x0040
  108. #define TBIANA_FULL_DUPLEX 0x0020
  109. #define TBICR_PHY_RESET 0x8000
  110. #define TBICR_ANEG_ENABLE 0x1000
  111. #define TBICR_RESTART_ANEG 0x0200
  112. #define TBICR_FULL_DUPLEX 0x0100
  113. #define TBICR_SPEED1_SET 0x0040
  114. /* IEVENT - interrupt events register */
  115. #define IEVENT_BABR 0x80000000 /* Babbling receive error */
  116. #define IEVENT_RXC 0x40000000 /* pause control frame received */
  117. #define IEVENT_MSRO 0x04000000 /* MIB counter overflow */
  118. #define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */
  119. #define IEVENT_BABT 0x01000000 /* Babbling transmit error */
  120. #define IEVENT_TXC 0x00800000 /* control frame transmitted */
  121. #define IEVENT_TXE 0x00400000 /* Transmit channel error */
  122. #define IEVENT_LC 0x00040000 /* Late collision occurred */
  123. #define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */
  124. #define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */
  125. #define IEVENT_ABRT 0x00008000 /* Transmit packet abort */
  126. #define IEVENT_MMRD 0x00000400 /* MII management read complete */
  127. #define IEVENT_MMWR 0x00000200 /* MII management write complete */
  128. #define IEVENT_GRSC 0x00000100 /* Graceful stop complete */
  129. #define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */
  130. #define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */
  131. #define IEVENT_CLEAR_ALL 0xffffffff
  132. /* IMASK - interrupt mask register */
  133. #define IMASK_BREN 0x80000000 /* Babbling receive enable */
  134. #define IMASK_RXCEN 0x40000000 /* receive control enable */
  135. #define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */
  136. #define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */
  137. #define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */
  138. #define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */
  139. #define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */
  140. #define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */
  141. #define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */
  142. #define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */
  143. #define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */
  144. #define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */
  145. #define IMASK_MMWREN 0x00000200 /* MII management write complete enable */
  146. #define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */
  147. #define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */
  148. #define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */
  149. #define IMASK_MASK_ALL 0x00000000
  150. /* ECNTRL - ethernet control register */
  151. #define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
  152. #define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */
  153. #define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */
  154. #define ECNTRL_STEN 0x00001000 /* enable internal counters to update */
  155. #define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */
  156. #define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */
  157. #define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */
  158. #define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
  159. 0- RGMII 10 Mbps, SGMII 10 Mbps */
  160. #define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */
  161. #define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */
  162. #define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
  163. /* TCTRL - Transmit control register */
  164. #define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */
  165. #define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */
  166. #define TCTRL_GTS 0x00000020 /* Graceful transmit stop */
  167. #define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */
  168. /* RCTRL - Receive control register */
  169. #define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */
  170. #define RCTRL_PAL_SHIFT 16
  171. #define RCTRL_CFA 0x00008000 /* control frame accept enable */
  172. #define RCTRL_GHTX 0x00000800 /* group address hash table extend */
  173. #define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */
  174. #define RCTRL_GRS 0x00000020 /* graceful receive stop */
  175. #define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */
  176. #define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */
  177. #define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */
  178. #define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */
  179. #define RCTRL_UPROM 0x00000001 /* all unicast frame received */
  180. /* MACCFG1 - MAC configuration 1 register */
  181. #define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */
  182. #define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */
  183. #define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */
  184. #define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */
  185. #define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */
  186. #define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */
  187. #define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */
  188. #define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */
  189. #define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */
  190. #define MACCFG1_RX_EN 0x00000004 /* Rx enable */
  191. #define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */
  192. #define MACCFG1_TX_EN 0x00000001 /* Tx enable */
  193. #define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN)
  194. /* MACCFG2 - MAC configuration 2 register */
  195. #define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */
  196. #define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK)
  197. #define MACCFG2_IF_MODE_MASK 0x00000300
  198. #define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */
  199. #define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */
  200. #define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */
  201. #define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */
  202. #define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */
  203. #define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */
  204. #define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */
  205. #define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */
  206. #define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */
  207. #define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */
  208. struct fsl_enet_mac;
  209. void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
  210. int max_rx_len);
  211. #endif