fsl_ddr_sdram.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017-2018 NXP Semiconductor
  5. */
  6. #ifndef FSL_DDR_MEMCTL_H
  7. #define FSL_DDR_MEMCTL_H
  8. /*
  9. * Pick a basic DDR Technology.
  10. */
  11. #include <ddr_spd.h>
  12. #include <fsl_ddrc_version.h>
  13. #define SDRAM_TYPE_DDR1 2
  14. #define SDRAM_TYPE_DDR2 3
  15. #define SDRAM_TYPE_LPDDR1 6
  16. #define SDRAM_TYPE_DDR3 7
  17. #define SDRAM_TYPE_DDR4 5
  18. #define DDR_BL4 4 /* burst length 4 */
  19. #define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */
  20. #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
  21. #define DDR_BL8 8 /* burst length 8 */
  22. #define DDR3_RTT_OFF 0
  23. #define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
  24. #define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
  25. #define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
  26. #define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
  27. #define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
  28. #define DDR4_RTT_OFF 0
  29. #define DDR4_RTT_60_OHM 1 /* RZQ/4 */
  30. #define DDR4_RTT_120_OHM 2 /* RZQ/2 */
  31. #define DDR4_RTT_40_OHM 3 /* RZQ/6 */
  32. #define DDR4_RTT_240_OHM 4 /* RZQ/1 */
  33. #define DDR4_RTT_48_OHM 5 /* RZQ/5 */
  34. #define DDR4_RTT_80_OHM 6 /* RZQ/3 */
  35. #define DDR4_RTT_34_OHM 7 /* RZQ/7 */
  36. #define DDR2_RTT_OFF 0
  37. #define DDR2_RTT_75_OHM 1
  38. #define DDR2_RTT_150_OHM 2
  39. #define DDR2_RTT_50_OHM 3
  40. #if defined(CONFIG_SYS_FSL_DDR1)
  41. #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
  42. typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
  43. #ifndef CONFIG_FSL_SDRAM_TYPE
  44. #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1
  45. #endif
  46. #elif defined(CONFIG_SYS_FSL_DDR2)
  47. #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
  48. typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
  49. #ifndef CONFIG_FSL_SDRAM_TYPE
  50. #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
  51. #endif
  52. #elif defined(CONFIG_SYS_FSL_DDR3)
  53. typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
  54. #ifndef CONFIG_FSL_SDRAM_TYPE
  55. #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
  56. #endif
  57. #elif defined(CONFIG_SYS_FSL_DDR4)
  58. #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */
  59. typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
  60. #ifndef CONFIG_FSL_SDRAM_TYPE
  61. #define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR4
  62. #endif
  63. #endif /* #if defined(CONFIG_SYS_FSL_DDR1) */
  64. #define FSL_DDR_ODT_NEVER 0x0
  65. #define FSL_DDR_ODT_CS 0x1
  66. #define FSL_DDR_ODT_ALL_OTHER_CS 0x2
  67. #define FSL_DDR_ODT_OTHER_DIMM 0x3
  68. #define FSL_DDR_ODT_ALL 0x4
  69. #define FSL_DDR_ODT_SAME_DIMM 0x5
  70. #define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
  71. #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
  72. /* define bank(chip select) interleaving mode */
  73. #define FSL_DDR_CS0_CS1 0x40
  74. #define FSL_DDR_CS2_CS3 0x20
  75. #define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
  76. #define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
  77. /* define memory controller interleaving mode */
  78. #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
  79. #define FSL_DDR_PAGE_INTERLEAVING 0x1
  80. #define FSL_DDR_BANK_INTERLEAVING 0x2
  81. #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
  82. #define FSL_DDR_256B_INTERLEAVING 0x8
  83. #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
  84. #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
  85. #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
  86. /* placeholder for 4-way interleaving */
  87. #define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A
  88. #define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
  89. #define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
  90. #define SDRAM_CS_CONFIG_EN 0x80000000
  91. /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  92. */
  93. #define SDRAM_CFG_MEM_EN 0x80000000
  94. #define SDRAM_CFG_SREN 0x40000000
  95. #define SDRAM_CFG_ECC_EN 0x20000000
  96. #define SDRAM_CFG_RD_EN 0x10000000
  97. #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
  98. #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
  99. #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
  100. #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
  101. #define SDRAM_CFG_DYN_PWR 0x00200000
  102. #define SDRAM_CFG_DBW_MASK 0x00180000
  103. #define SDRAM_CFG_DBW_SHIFT 19
  104. #define SDRAM_CFG_32_BE 0x00080000
  105. #define SDRAM_CFG_16_BE 0x00100000
  106. #define SDRAM_CFG_8_BE 0x00040000
  107. #define SDRAM_CFG_NCAP 0x00020000
  108. #define SDRAM_CFG_2T_EN 0x00008000
  109. #define SDRAM_CFG_BI 0x00000001
  110. #define SDRAM_CFG2_FRC_SR 0x80000000
  111. #define SDRAM_CFG2_D_INIT 0x00000010
  112. #define SDRAM_CFG2_AP_EN 0x00000020
  113. #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
  114. #define SDRAM_CFG2_ODT_NEVER 0
  115. #define SDRAM_CFG2_ODT_ONLY_WRITE 1
  116. #define SDRAM_CFG2_ODT_ONLY_READ 2
  117. #define SDRAM_CFG2_ODT_ALWAYS 3
  118. #define SDRAM_INTERVAL_BSTOPRE 0x3FFF
  119. #define TIMING_CFG_2_CPO_MASK 0x0F800000
  120. #if defined(CONFIG_SYS_FSL_DDR_VER) && \
  121. (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
  122. #define RD_TO_PRE_MASK 0xf
  123. #define RD_TO_PRE_SHIFT 13
  124. #define WR_DATA_DELAY_MASK 0xf
  125. #define WR_DATA_DELAY_SHIFT 9
  126. #else
  127. #define RD_TO_PRE_MASK 0x7
  128. #define RD_TO_PRE_SHIFT 13
  129. #define WR_DATA_DELAY_MASK 0x7
  130. #define WR_DATA_DELAY_SHIFT 10
  131. #endif
  132. /* DDR_EOR register */
  133. #define DDR_EOR_RD_REOD_DIS 0x07000000
  134. #define DDR_EOR_WD_REOD_DIS 0x00100000
  135. /* DDR_MD_CNTL */
  136. #define MD_CNTL_MD_EN 0x80000000
  137. #define MD_CNTL_CS_SEL_CS0 0x00000000
  138. #define MD_CNTL_CS_SEL_CS1 0x10000000
  139. #define MD_CNTL_CS_SEL_CS2 0x20000000
  140. #define MD_CNTL_CS_SEL_CS3 0x30000000
  141. #define MD_CNTL_CS_SEL_CS0_CS1 0x40000000
  142. #define MD_CNTL_CS_SEL_CS2_CS3 0x50000000
  143. #define MD_CNTL_MD_SEL_MR 0x00000000
  144. #define MD_CNTL_MD_SEL_EMR 0x01000000
  145. #define MD_CNTL_MD_SEL_EMR2 0x02000000
  146. #define MD_CNTL_MD_SEL_EMR3 0x03000000
  147. #define MD_CNTL_SET_REF 0x00800000
  148. #define MD_CNTL_SET_PRE 0x00400000
  149. #define MD_CNTL_CKE_CNTL_LOW 0x00100000
  150. #define MD_CNTL_CKE_CNTL_HIGH 0x00200000
  151. #define MD_CNTL_WRCW 0x00080000
  152. #define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF)
  153. #define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
  154. #define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
  155. /* DDR_CDR1 */
  156. #define DDR_CDR1_DHC_EN 0x80000000
  157. #define DDR_CDR1_V0PT9_EN 0x40000000
  158. #define DDR_CDR1_ODT_SHIFT 17
  159. #define DDR_CDR1_ODT_MASK 0x6
  160. #define DDR_CDR2_ODT_MASK 0x1
  161. #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
  162. #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
  163. #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
  164. #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  165. #define DDR_CDR2_VREF_RANGE_2 0x00000040
  166. /* DDR ERR_DISABLE */
  167. #define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
  168. /* Mode Registers */
  169. #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
  170. #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
  171. /* DEBUG_26 register */
  172. #define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */
  173. #define DDR_CAS_TO_PRE_SUB_SHIFT 12
  174. /* DEBUG_29 register */
  175. #define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
  176. #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
  177. (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
  178. #ifdef CONFIG_SYS_FSL_DDR3L
  179. #define DDR_CDR_ODT_OFF 0x0
  180. #define DDR_CDR_ODT_120ohm 0x1
  181. #define DDR_CDR_ODT_200ohm 0x2
  182. #define DDR_CDR_ODT_75ohm 0x3
  183. #define DDR_CDR_ODT_60ohm 0x5
  184. #define DDR_CDR_ODT_46ohm 0x7
  185. #elif defined(CONFIG_SYS_FSL_DDR4)
  186. #define DDR_CDR_ODT_OFF 0x0
  187. #define DDR_CDR_ODT_100ohm 0x1
  188. #define DDR_CDR_ODT_120OHM 0x2
  189. #define DDR_CDR_ODT_80ohm 0x3
  190. #define DDR_CDR_ODT_60ohm 0x4
  191. #define DDR_CDR_ODT_40ohm 0x5
  192. #define DDR_CDR_ODT_50ohm 0x6
  193. #define DDR_CDR_ODT_30ohm 0x7
  194. #else
  195. #define DDR_CDR_ODT_OFF 0x0
  196. #define DDR_CDR_ODT_120ohm 0x1
  197. #define DDR_CDR_ODT_180ohm 0x2
  198. #define DDR_CDR_ODT_75ohm 0x3
  199. #define DDR_CDR_ODT_110ohm 0x4
  200. #define DDR_CDR_ODT_60hm 0x5
  201. #define DDR_CDR_ODT_70ohm 0x6
  202. #define DDR_CDR_ODT_47ohm 0x7
  203. #endif /* DDR3L */
  204. #else
  205. #define DDR_CDR_ODT_75ohm 0x0
  206. #define DDR_CDR_ODT_55ohm 0x1
  207. #define DDR_CDR_ODT_60ohm 0x2
  208. #define DDR_CDR_ODT_50ohm 0x3
  209. #define DDR_CDR_ODT_150ohm 0x4
  210. #define DDR_CDR_ODT_43ohm 0x5
  211. #define DDR_CDR_ODT_120ohm 0x6
  212. #endif
  213. #define DDR_INIT_ADDR_EXT_UIA (1 << 31)
  214. /* Record of register values computed */
  215. typedef struct fsl_ddr_cfg_regs_s {
  216. struct {
  217. unsigned int bnds;
  218. unsigned int config;
  219. unsigned int config_2;
  220. } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
  221. unsigned int timing_cfg_3;
  222. unsigned int timing_cfg_0;
  223. unsigned int timing_cfg_1;
  224. unsigned int timing_cfg_2;
  225. unsigned int ddr_sdram_cfg;
  226. unsigned int ddr_sdram_cfg_2;
  227. unsigned int ddr_sdram_cfg_3;
  228. unsigned int ddr_sdram_mode;
  229. unsigned int ddr_sdram_mode_2;
  230. unsigned int ddr_sdram_mode_3;
  231. unsigned int ddr_sdram_mode_4;
  232. unsigned int ddr_sdram_mode_5;
  233. unsigned int ddr_sdram_mode_6;
  234. unsigned int ddr_sdram_mode_7;
  235. unsigned int ddr_sdram_mode_8;
  236. unsigned int ddr_sdram_mode_9;
  237. unsigned int ddr_sdram_mode_10;
  238. unsigned int ddr_sdram_mode_11;
  239. unsigned int ddr_sdram_mode_12;
  240. unsigned int ddr_sdram_mode_13;
  241. unsigned int ddr_sdram_mode_14;
  242. unsigned int ddr_sdram_mode_15;
  243. unsigned int ddr_sdram_mode_16;
  244. unsigned int ddr_sdram_md_cntl;
  245. unsigned int ddr_sdram_interval;
  246. unsigned int ddr_data_init;
  247. unsigned int ddr_sdram_clk_cntl;
  248. unsigned int ddr_init_addr;
  249. unsigned int ddr_init_ext_addr;
  250. unsigned int timing_cfg_4;
  251. unsigned int timing_cfg_5;
  252. unsigned int timing_cfg_6;
  253. unsigned int timing_cfg_7;
  254. unsigned int timing_cfg_8;
  255. unsigned int timing_cfg_9;
  256. unsigned int ddr_zq_cntl;
  257. unsigned int ddr_wrlvl_cntl;
  258. unsigned int ddr_wrlvl_cntl_2;
  259. unsigned int ddr_wrlvl_cntl_3;
  260. unsigned int ddr_sr_cntr;
  261. unsigned int ddr_sdram_rcw_1;
  262. unsigned int ddr_sdram_rcw_2;
  263. unsigned int ddr_sdram_rcw_3;
  264. unsigned int ddr_sdram_rcw_4;
  265. unsigned int ddr_sdram_rcw_5;
  266. unsigned int ddr_sdram_rcw_6;
  267. unsigned int dq_map_0;
  268. unsigned int dq_map_1;
  269. unsigned int dq_map_2;
  270. unsigned int dq_map_3;
  271. unsigned int ddr_eor;
  272. unsigned int ddr_cdr1;
  273. unsigned int ddr_cdr2;
  274. unsigned int err_disable;
  275. unsigned int err_int_en;
  276. unsigned int debug[64];
  277. } fsl_ddr_cfg_regs_t;
  278. typedef struct memctl_options_partial_s {
  279. unsigned int all_dimms_ecc_capable;
  280. unsigned int all_dimms_tckmax_ps;
  281. unsigned int all_dimms_burst_lengths_bitmask;
  282. unsigned int all_dimms_registered;
  283. unsigned int all_dimms_unbuffered;
  284. /* unsigned int lowest_common_spd_caslat; */
  285. unsigned int all_dimms_minimum_trcd_ps;
  286. } memctl_options_partial_t;
  287. #define DDR_DATA_BUS_WIDTH_64 0
  288. #define DDR_DATA_BUS_WIDTH_32 1
  289. #define DDR_DATA_BUS_WIDTH_16 2
  290. #define DDR_CSWL_CS0 0x04000001
  291. /*
  292. * Generalized parameters for memory controller configuration,
  293. * might be a little specific to the FSL memory controller
  294. */
  295. typedef struct memctl_options_s {
  296. /*
  297. * Memory organization parameters
  298. *
  299. * if DIMM is present in the system
  300. * where DIMMs are with respect to chip select
  301. * where chip selects are with respect to memory boundaries
  302. */
  303. unsigned int registered_dimm_en; /* use registered DIMM support */
  304. /* Options local to a Chip Select */
  305. struct cs_local_opts_s {
  306. unsigned int auto_precharge;
  307. unsigned int odt_rd_cfg;
  308. unsigned int odt_wr_cfg;
  309. unsigned int odt_rtt_norm;
  310. unsigned int odt_rtt_wr;
  311. } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
  312. /* Special configurations for chip select */
  313. unsigned int memctl_interleaving;
  314. unsigned int memctl_interleaving_mode;
  315. unsigned int ba_intlv_ctl;
  316. unsigned int addr_hash;
  317. /* Operational mode parameters */
  318. unsigned int ecc_mode; /* Use ECC? */
  319. /* Initialize ECC using memory controller? */
  320. unsigned int ecc_init_using_memctl;
  321. unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
  322. /* SREN - self-refresh during sleep */
  323. unsigned int self_refresh_in_sleep;
  324. /* SR_IE - Self-refresh interrupt enable */
  325. unsigned int self_refresh_interrupt_en;
  326. unsigned int dynamic_power; /* DYN_PWR */
  327. /* memory data width to use (16-bit, 32-bit, 64-bit) */
  328. unsigned int data_bus_width;
  329. unsigned int burst_length; /* BL4, OTF and BL8 */
  330. /* On-The-Fly Burst Chop enable */
  331. unsigned int otf_burst_chop_en;
  332. /* mirrior DIMMs for DDR3 */
  333. unsigned int mirrored_dimm;
  334. unsigned int quad_rank_present;
  335. unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
  336. unsigned int x4_en; /* enable x4 devices */
  337. unsigned int package_3ds;
  338. /* Global Timing Parameters */
  339. unsigned int cas_latency_override;
  340. unsigned int cas_latency_override_value;
  341. unsigned int use_derated_caslat;
  342. unsigned int additive_latency_override;
  343. unsigned int additive_latency_override_value;
  344. unsigned int clk_adjust; /* */
  345. unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
  346. unsigned int cpo_sample; /* optimize debug_29[24:31] */
  347. unsigned int write_data_delay; /* DQS adjust */
  348. unsigned int cswl_override;
  349. unsigned int wrlvl_override;
  350. unsigned int wrlvl_sample; /* Write leveling */
  351. unsigned int wrlvl_start;
  352. unsigned int wrlvl_ctl_2;
  353. unsigned int wrlvl_ctl_3;
  354. unsigned int half_strength_driver_enable;
  355. unsigned int twot_en;
  356. unsigned int threet_en;
  357. unsigned int bstopre;
  358. unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
  359. /* Rtt impedance */
  360. unsigned int rtt_override; /* rtt_override enable */
  361. unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
  362. unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
  363. /* Automatic self refresh */
  364. unsigned int auto_self_refresh_en;
  365. unsigned int sr_it;
  366. /* ZQ calibration */
  367. unsigned int zq_en;
  368. /* Write leveling */
  369. unsigned int wrlvl_en;
  370. /* RCW override for RDIMM */
  371. unsigned int rcw_override;
  372. unsigned int rcw_1;
  373. unsigned int rcw_2;
  374. unsigned int rcw_3;
  375. /* control register 1 */
  376. unsigned int ddr_cdr1;
  377. unsigned int ddr_cdr2;
  378. unsigned int trwt_override;
  379. unsigned int trwt; /* read-to-write turnaround */
  380. } memctl_options_t;
  381. phys_size_t fsl_ddr_sdram(void);
  382. phys_size_t fsl_ddr_sdram_size(void);
  383. phys_size_t fsl_other_ddr_sdram(unsigned long long base,
  384. unsigned int first_ctrl,
  385. unsigned int num_ctrls,
  386. unsigned int dimm_slots_per_ctrl,
  387. int (*board_need_reset)(void),
  388. void (*board_reset)(void),
  389. void (*board_de_reset)(void));
  390. extern int fsl_use_spd(void);
  391. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  392. unsigned int ctrl_num, int step);
  393. u32 fsl_ddr_get_intl3r(void);
  394. void print_ddr_info(unsigned int start_ctrl);
  395. static void __board_assert_mem_reset(void)
  396. {
  397. }
  398. static void __board_deassert_mem_reset(void)
  399. {
  400. }
  401. void board_assert_mem_reset(void)
  402. __attribute__((weak, alias("__board_assert_mem_reset")));
  403. void board_deassert_mem_reset(void)
  404. __attribute__((weak, alias("__board_deassert_mem_reset")));
  405. static int __board_need_mem_reset(void)
  406. {
  407. return 0;
  408. }
  409. int board_need_mem_reset(void)
  410. __attribute__((weak, alias("__board_need_mem_reset")));
  411. #if defined(CONFIG_DEEP_SLEEP)
  412. void board_mem_sleep_setup(void);
  413. bool is_warm_boot(void);
  414. int fsl_dp_resume(void);
  415. #endif
  416. /*
  417. * The 85xx boards have a common prototype for fixed_sdram so put the
  418. * declaration here.
  419. */
  420. #ifdef CONFIG_MPC85xx
  421. extern phys_size_t fixed_sdram(void);
  422. #endif
  423. #if defined(CONFIG_DDR_ECC)
  424. extern void ddr_enable_ecc(unsigned int dram_size);
  425. #endif
  426. typedef struct fixed_ddr_parm{
  427. int min_freq;
  428. int max_freq;
  429. fsl_ddr_cfg_regs_t *ddr_settings;
  430. } fixed_ddr_parm_t;
  431. /**
  432. * fsl_initdram() - Set up the SDRAM
  433. *
  434. * @return 0 if OK, -ve on error
  435. */
  436. int fsl_initdram(void);
  437. #endif