fsl_ddr.h 4.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2008-2014 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef FSL_DDR_MAIN_H
  6. #define FSL_DDR_MAIN_H
  7. #include <fsl_ddrc_version.h>
  8. #include <fsl_ddr_sdram.h>
  9. #include <fsl_ddr_dimm_params.h>
  10. #include <common_timing_params.h>
  11. struct cmd_tbl;
  12. #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  13. /* All controllers are for main memory */
  14. #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
  15. #endif
  16. #ifdef CONFIG_SYS_FSL_DDR_LE
  17. #define ddr_in32(a) in_le32(a)
  18. #define ddr_out32(a, v) out_le32(a, v)
  19. #define ddr_setbits32(a, v) setbits_le32(a, v)
  20. #define ddr_clrbits32(a, v) clrbits_le32(a, v)
  21. #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  22. #else
  23. #define ddr_in32(a) in_be32(a)
  24. #define ddr_out32(a, v) out_be32(a, v)
  25. #define ddr_setbits32(a, v) setbits_be32(a, v)
  26. #define ddr_clrbits32(a, v) clrbits_be32(a, v)
  27. #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  28. #endif
  29. u32 fsl_ddr_get_version(unsigned int ctrl_num);
  30. #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  31. /*
  32. * Bind the main DDR setup driver's generic names
  33. * to this specific DDR technology.
  34. */
  35. static __inline__ int
  36. compute_dimm_parameters(const unsigned int ctrl_num,
  37. const generic_spd_eeprom_t *spd,
  38. dimm_params_t *pdimm,
  39. unsigned int dimm_number)
  40. {
  41. return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
  42. }
  43. #endif
  44. /*
  45. * Data Structures
  46. *
  47. * All data structures have to be on the stack
  48. */
  49. #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  50. typedef struct {
  51. generic_spd_eeprom_t
  52. spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  53. struct dimm_params_s
  54. dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  55. memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  56. common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  57. fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  58. unsigned int first_ctrl;
  59. unsigned int num_ctrls;
  60. unsigned long long mem_base;
  61. unsigned int dimm_slots_per_ctrl;
  62. int (*board_need_mem_reset)(void);
  63. void (*board_mem_reset)(void);
  64. void (*board_mem_de_reset)(void);
  65. } fsl_ddr_info_t;
  66. /* Compute steps */
  67. #define STEP_GET_SPD (1 << 0)
  68. #define STEP_COMPUTE_DIMM_PARMS (1 << 1)
  69. #define STEP_COMPUTE_COMMON_PARMS (1 << 2)
  70. #define STEP_GATHER_OPTS (1 << 3)
  71. #define STEP_ASSIGN_ADDRESSES (1 << 4)
  72. #define STEP_COMPUTE_REGS (1 << 5)
  73. #define STEP_PROGRAM_REGS (1 << 6)
  74. #define STEP_ALL 0xFFF
  75. unsigned long long
  76. fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  77. unsigned int size_only);
  78. const char *step_to_string(unsigned int step);
  79. unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
  80. const memctl_options_t *popts,
  81. fsl_ddr_cfg_regs_t *ddr,
  82. const common_timing_params_t *common_dimm,
  83. const dimm_params_t *dimm_parameters,
  84. unsigned int dbw_capacity_adjust,
  85. unsigned int size_only);
  86. unsigned int compute_lowest_common_dimm_parameters(
  87. const unsigned int ctrl_num,
  88. const dimm_params_t *dimm_params,
  89. common_timing_params_t *outpdimm,
  90. unsigned int number_of_dimms);
  91. unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
  92. memctl_options_t *popts,
  93. dimm_params_t *pdimm,
  94. unsigned int ctrl_num);
  95. void check_interleaving_options(fsl_ddr_info_t *pinfo);
  96. unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
  97. unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
  98. unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
  99. void fsl_ddr_set_lawbar(
  100. const common_timing_params_t *memctl_common_params,
  101. unsigned int memctl_interleaved,
  102. unsigned int ctrl_num);
  103. void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
  104. unsigned int last_ctrl);
  105. int fsl_ddr_interactive_env_var_exists(void);
  106. unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
  107. void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  108. unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
  109. int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
  110. unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
  111. void board_add_ram_info(int use_default);
  112. /* processor specific function */
  113. void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  114. unsigned int ctrl_num, int step);
  115. void remove_unused_controllers(fsl_ddr_info_t *info);
  116. /* board specific function */
  117. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  118. unsigned int controller_number,
  119. unsigned int dimm_number);
  120. void update_spd_address(unsigned int ctrl_num,
  121. unsigned int slot,
  122. unsigned int *addr);
  123. void erratum_a009942_check_cpo(void);
  124. #endif