ftahbc020s.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Andes Technology Corporation
  4. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  5. */
  6. /* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
  7. #ifndef __FTAHBC020S_H
  8. #define __FTAHBC202S_H
  9. /* Registers Offsets */
  10. /*
  11. * AHB Slave BSR, offset: n * 4, n=0~31
  12. */
  13. #ifndef __ASSEMBLY__
  14. struct ftahbc02s {
  15. unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */
  16. unsigned int pcr; /* 0x80 - Priority Ctrl Reg */
  17. unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */
  18. unsigned int cr; /* 0x88 - Ctrl Reg */
  19. };
  20. #endif /* __ASSEMBLY__ */
  21. /*
  22. * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
  23. */
  24. #define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20)
  25. #define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16)
  26. /* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
  27. #define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */
  28. /*
  29. * FTAHBC020S_PCR - Priority Control Register
  30. */
  31. #define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */
  32. /*
  33. * FTAHBC020S_CR - Interrupt Control Register
  34. */
  35. #define FTAHBC020S_CR_INTSTS (1 << 24)
  36. #define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20)
  37. #define FTAHBC020S_CR_INTSMASK (1 << 16)
  38. #define FTAHBC020S_CR_REMAP (1 << 0)
  39. #endif /* __FTAHBC020S_H */