dw_hdmi.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  6. * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  7. */
  8. #ifndef _DW_HDMI_H
  9. #define _DW_HDMI_H
  10. #include <edid.h>
  11. #define HDMI_EDID_BLOCK_SIZE 128
  12. /* Identification Registers */
  13. #define HDMI_DESIGN_ID 0x0000
  14. #define HDMI_REVISION_ID 0x0001
  15. #define HDMI_PRODUCT_ID0 0x0002
  16. #define HDMI_PRODUCT_ID1 0x0003
  17. #define HDMI_CONFIG0_ID 0x0004
  18. #define HDMI_CONFIG1_ID 0x0005
  19. #define HDMI_CONFIG2_ID 0x0006
  20. #define HDMI_CONFIG3_ID 0x0007
  21. /* Interrupt Registers */
  22. #define HDMI_IH_FC_STAT0 0x0100
  23. #define HDMI_IH_FC_STAT1 0x0101
  24. #define HDMI_IH_FC_STAT2 0x0102
  25. #define HDMI_IH_AS_STAT0 0x0103
  26. #define HDMI_IH_PHY_STAT0 0x0104
  27. #define HDMI_IH_I2CM_STAT0 0x0105
  28. #define HDMI_IH_CEC_STAT0 0x0106
  29. #define HDMI_IH_VP_STAT0 0x0107
  30. #define HDMI_IH_I2CMPHY_STAT0 0x0108
  31. #define HDMI_IH_AHBDMAAUD_STAT0 0x0109
  32. #define HDMI_IH_MUTE_FC_STAT0 0x0180
  33. #define HDMI_IH_MUTE_FC_STAT1 0x0181
  34. #define HDMI_IH_MUTE_FC_STAT2 0x0182
  35. #define HDMI_IH_MUTE_AS_STAT0 0x0183
  36. #define HDMI_IH_MUTE_PHY_STAT0 0x0184
  37. #define HDMI_IH_MUTE_I2CM_STAT0 0x0185
  38. #define HDMI_IH_MUTE_CEC_STAT0 0x0186
  39. #define HDMI_IH_MUTE_VP_STAT0 0x0187
  40. #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
  41. #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
  42. #define HDMI_IH_MUTE 0x01FF
  43. /* Video Sample Registers */
  44. #define HDMI_TX_INVID0 0x0200
  45. #define HDMI_TX_INSTUFFING 0x0201
  46. #define HDMI_TX_GYDATA0 0x0202
  47. #define HDMI_TX_GYDATA1 0x0203
  48. #define HDMI_TX_RCRDATA0 0x0204
  49. #define HDMI_TX_RCRDATA1 0x0205
  50. #define HDMI_TX_BCBDATA0 0x0206
  51. #define HDMI_TX_BCBDATA1 0x0207
  52. /* Video Packetizer Registers */
  53. #define HDMI_VP_STATUS 0x0800
  54. #define HDMI_VP_PR_CD 0x0801
  55. #define HDMI_VP_STUFF 0x0802
  56. #define HDMI_VP_REMAP 0x0803
  57. #define HDMI_VP_CONF 0x0804
  58. #define HDMI_VP_STAT 0x0805
  59. #define HDMI_VP_INT 0x0806
  60. #define HDMI_VP_MASK 0x0807
  61. #define HDMI_VP_POL 0x0808
  62. /* Frame Composer Registers */
  63. #define HDMI_FC_INVIDCONF 0x1000
  64. #define HDMI_FC_INHACTV0 0x1001
  65. #define HDMI_FC_INHACTV1 0x1002
  66. #define HDMI_FC_INHBLANK0 0x1003
  67. #define HDMI_FC_INHBLANK1 0x1004
  68. #define HDMI_FC_INVACTV0 0x1005
  69. #define HDMI_FC_INVACTV1 0x1006
  70. #define HDMI_FC_INVBLANK 0x1007
  71. #define HDMI_FC_HSYNCINDELAY0 0x1008
  72. #define HDMI_FC_HSYNCINDELAY1 0x1009
  73. #define HDMI_FC_HSYNCINWIDTH0 0x100A
  74. #define HDMI_FC_HSYNCINWIDTH1 0x100B
  75. #define HDMI_FC_VSYNCINDELAY 0x100C
  76. #define HDMI_FC_VSYNCINWIDTH 0x100D
  77. #define HDMI_FC_INFREQ0 0x100E
  78. #define HDMI_FC_INFREQ1 0x100F
  79. #define HDMI_FC_INFREQ2 0x1010
  80. #define HDMI_FC_CTRLDUR 0x1011
  81. #define HDMI_FC_EXCTRLDUR 0x1012
  82. #define HDMI_FC_EXCTRLSPAC 0x1013
  83. #define HDMI_FC_CH0PREAM 0x1014
  84. #define HDMI_FC_CH1PREAM 0x1015
  85. #define HDMI_FC_CH2PREAM 0x1016
  86. #define HDMI_FC_AVICONF3 0x1017
  87. #define HDMI_FC_GCP 0x1018
  88. #define HDMI_FC_AVICONF0 0x1019
  89. #define HDMI_FC_AVICONF1 0x101A
  90. #define HDMI_FC_AVICONF2 0x101B
  91. #define HDMI_FC_AVIVID 0x101C
  92. #define HDMI_FC_AVIETB0 0x101D
  93. #define HDMI_FC_AVIETB1 0x101E
  94. #define HDMI_FC_AVISBB0 0x101F
  95. #define HDMI_FC_AVISBB1 0x1020
  96. #define HDMI_FC_AVIELB0 0x1021
  97. #define HDMI_FC_AVIELB1 0x1022
  98. #define HDMI_FC_AVISRB0 0x1023
  99. #define HDMI_FC_AVISRB1 0x1024
  100. #define HDMI_FC_AUDICONF0 0x1025
  101. #define HDMI_FC_AUDICONF1 0x1026
  102. #define HDMI_FC_AUDICONF2 0x1027
  103. #define HDMI_FC_AUDICONF3 0x1028
  104. #define HDMI_FC_VSDIEEEID0 0x1029
  105. #define HDMI_FC_VSDSIZE 0x102A
  106. /* HDMI Source PHY Registers */
  107. #define HDMI_PHY_CONF0 0x3000
  108. #define HDMI_PHY_TST0 0x3001
  109. #define HDMI_PHY_TST1 0x3002
  110. #define HDMI_PHY_TST2 0x3003
  111. #define HDMI_PHY_STAT0 0x3004
  112. #define HDMI_PHY_INT0 0x3005
  113. #define HDMI_PHY_MASK0 0x3006
  114. #define HDMI_PHY_POL0 0x3007
  115. /* HDMI Master PHY Registers */
  116. #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
  117. #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
  118. #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
  119. #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
  120. #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
  121. #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
  122. #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
  123. #define HDMI_PHY_I2CM_INT_ADDR 0x3027
  124. #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
  125. #define HDMI_PHY_I2CM_DIV_ADDR 0x3029
  126. #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
  127. #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
  128. #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
  129. #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
  130. #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
  131. #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
  132. #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
  133. #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
  134. #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
  135. /* Audio Sampler Registers */
  136. #define HDMI_AUD_CONF0 0x3100
  137. #define HDMI_AUD_CONF1 0x3101
  138. #define HDMI_AUD_INT 0x3102
  139. #define HDMI_AUD_CONF2 0x3103
  140. #define HDMI_AUD_INT1 0x3104
  141. #define HDMI_AUD_N1 0x3200
  142. #define HDMI_AUD_N2 0x3201
  143. #define HDMI_AUD_N3 0x3202
  144. #define HDMI_AUD_CTS1 0x3203
  145. #define HDMI_AUD_CTS2 0x3204
  146. #define HDMI_AUD_CTS3 0x3205
  147. #define HDMI_AUD_INPUTCLKFS 0x3206
  148. #define HDMI_AUD_SPDIFINT 0x3302
  149. #define HDMI_AUD_CONF0_HBR 0x3400
  150. #define HDMI_AUD_HBR_STATUS 0x3401
  151. #define HDMI_AUD_HBR_INT 0x3402
  152. #define HDMI_AUD_HBR_POL 0x3403
  153. #define HDMI_AUD_HBR_MASK 0x3404
  154. /* Main Controller Registers */
  155. #define HDMI_MC_SFRDIV 0x4000
  156. #define HDMI_MC_CLKDIS 0x4001
  157. #define HDMI_MC_SWRSTZ 0x4002
  158. #define HDMI_MC_OPCTRL 0x4003
  159. #define HDMI_MC_FLOWCTRL 0x4004
  160. #define HDMI_MC_PHYRSTZ 0x4005
  161. #define HDMI_MC_LOCKONCLOCK 0x4006
  162. #define HDMI_MC_HEACPHY_RST 0x4007
  163. /* Color Space Converter Registers */
  164. #define HDMI_CSC_CFG 0x4100
  165. #define HDMI_CSC_SCALE 0x4101
  166. #define HDMI_CSC_COEF_A1_MSB 0x4102
  167. #define HDMI_CSC_COEF_A1_LSB 0x4103
  168. #define HDMI_CSC_COEF_A2_MSB 0x4104
  169. #define HDMI_CSC_COEF_A2_LSB 0x4105
  170. #define HDMI_CSC_COEF_A3_MSB 0x4106
  171. #define HDMI_CSC_COEF_A3_LSB 0x4107
  172. #define HDMI_CSC_COEF_A4_MSB 0x4108
  173. #define HDMI_CSC_COEF_A4_LSB 0x4109
  174. #define HDMI_CSC_COEF_B1_MSB 0x410A
  175. #define HDMI_CSC_COEF_B1_LSB 0x410B
  176. #define HDMI_CSC_COEF_B2_MSB 0x410C
  177. #define HDMI_CSC_COEF_B2_LSB 0x410D
  178. #define HDMI_CSC_COEF_B3_MSB 0x410E
  179. #define HDMI_CSC_COEF_B3_LSB 0x410F
  180. #define HDMI_CSC_COEF_B4_MSB 0x4110
  181. #define HDMI_CSC_COEF_B4_LSB 0x4111
  182. #define HDMI_CSC_COEF_C1_MSB 0x4112
  183. #define HDMI_CSC_COEF_C1_LSB 0x4113
  184. #define HDMI_CSC_COEF_C2_MSB 0x4114
  185. #define HDMI_CSC_COEF_C2_LSB 0x4115
  186. #define HDMI_CSC_COEF_C3_MSB 0x4116
  187. #define HDMI_CSC_COEF_C3_LSB 0x4117
  188. #define HDMI_CSC_COEF_C4_MSB 0x4118
  189. #define HDMI_CSC_COEF_C4_LSB 0x4119
  190. /* I2C Master Registers (E-DDC) */
  191. #define HDMI_I2CM_SLAVE 0x7E00
  192. #define HDMI_I2CM_ADDRESS 0x7E01
  193. #define HDMI_I2CM_DATAO 0x7E02
  194. #define HDMI_I2CM_DATAI 0x7E03
  195. #define HDMI_I2CM_OPERATION 0x7E04
  196. #define HDMI_I2CM_INT 0x7E05
  197. #define HDMI_I2CM_CTLINT 0x7E06
  198. #define HDMI_I2CM_DIV 0x7E07
  199. #define HDMI_I2CM_SEGADDR 0x7E08
  200. #define HDMI_I2CM_SOFTRSTZ 0x7E09
  201. #define HDMI_I2CM_SEGPTR 0x7E0A
  202. #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
  203. #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
  204. #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
  205. #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
  206. #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
  207. #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
  208. #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
  209. #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
  210. #define HDMI_I2CM_BUF0 0x7E20
  211. enum {
  212. /* HDMI PHY registers define */
  213. PHY_OPMODE_PLLCFG = 0x06,
  214. PHY_CKCALCTRL = 0x05,
  215. PHY_CKSYMTXCTRL = 0x09,
  216. PHY_VLEVCTRL = 0x0e,
  217. PHY_PLLCURRCTRL = 0x10,
  218. PHY_PLLPHBYCTRL = 0x13,
  219. PHY_PLLGMPCTRL = 0x15,
  220. PHY_PLLCLKBISTPHASE = 0x17,
  221. PHY_TXTERM = 0x19,
  222. /* ih_phy_stat0 field values */
  223. HDMI_IH_PHY_STAT0_HPD = 0x1,
  224. /* ih_mute field values */
  225. HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
  226. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
  227. /* tx_invid0 field values */
  228. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
  229. HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
  230. HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
  231. /* tx_instuffing field values */
  232. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
  233. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
  234. HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
  235. /* vp_pr_cd field values */
  236. HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
  237. HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
  238. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
  239. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
  240. /* vp_stuff field values */
  241. HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
  242. HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
  243. HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
  244. HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
  245. HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
  246. HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
  247. HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
  248. HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
  249. /* vp_conf field values */
  250. HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
  251. HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
  252. HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
  253. HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
  254. HDMI_VP_CONF_PR_EN_MASK = 0x10,
  255. HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
  256. HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
  257. HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
  258. HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
  259. HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
  260. HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
  261. HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
  262. /* vp_remap field values */
  263. HDMI_VP_REMAP_YCC422_16BIT = 0x0,
  264. /* fc_invidconf field values */
  265. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
  266. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
  267. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
  268. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
  269. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
  270. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  271. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
  272. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
  273. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  274. HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
  275. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
  276. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
  277. HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
  278. HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
  279. HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
  280. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
  281. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
  282. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
  283. HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
  284. HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
  285. HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
  286. /* fc_aviconf0-fc_aviconf3 field values */
  287. HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
  288. HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
  289. HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
  290. HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
  291. HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
  292. HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
  293. HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
  294. HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
  295. HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
  296. HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
  297. HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
  298. HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
  299. HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
  300. HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
  301. HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
  302. HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
  303. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
  304. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
  305. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
  306. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
  307. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
  308. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
  309. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
  310. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
  311. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
  312. HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
  313. HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
  314. HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
  315. HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
  316. HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
  317. HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
  318. HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
  319. HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
  320. HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
  321. HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
  322. HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
  323. HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
  324. HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
  325. HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
  326. HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
  327. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
  328. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
  329. HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
  330. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
  331. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
  332. HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
  333. HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
  334. HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
  335. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
  336. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
  337. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
  338. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
  339. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
  340. HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
  341. HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
  342. HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
  343. /* fc_gcp field values*/
  344. HDMI_FC_GCP_SET_AVMUTE = 0x02,
  345. HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
  346. /* phy_conf0 field values */
  347. HDMI_PHY_CONF0_PDZ_MASK = 0x80,
  348. HDMI_PHY_CONF0_PDZ_OFFSET = 7,
  349. HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
  350. HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
  351. HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
  352. HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
  353. HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
  354. HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
  355. HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
  356. HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
  357. HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
  358. HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
  359. HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
  360. HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
  361. /* phy_tst0 field values */
  362. HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
  363. HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
  364. /* phy_stat0 field values */
  365. HDMI_PHY_HPD = 0x02,
  366. HDMI_PHY_TX_PHY_LOCK = 0x01,
  367. /* phy_i2cm_slave_addr field values */
  368. HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
  369. /* phy_i2cm_operation_addr field values */
  370. HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
  371. /* hdmi_phy_i2cm_int_addr */
  372. HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
  373. /* hdmi_phy_i2cm_ctlint_addr */
  374. HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
  375. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
  376. /* aud_conf0 field values */
  377. HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
  378. HDMI_AUD_CONF0_I2S_SELECT = 0x20,
  379. HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
  380. HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
  381. HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
  382. HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
  383. /* aud_conf0 field values */
  384. HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
  385. HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
  386. /* aud_n3 field values */
  387. HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
  388. HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
  389. /* aud_cts3 field values */
  390. HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
  391. HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
  392. HDMI_AUD_CTS3_N_SHIFT_1 = 0,
  393. HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
  394. HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
  395. HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
  396. HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
  397. HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
  398. HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
  399. HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
  400. /* aud_inputclkfs filed values */
  401. HDMI_AUD_INPUTCLKFS_128 = 0x0,
  402. /* mc_clkdis field values */
  403. HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
  404. HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
  405. HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
  406. HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
  407. HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
  408. HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
  409. HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
  410. /* mc_swrstz field values */
  411. HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
  412. HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
  413. /* mc_flowctrl field values */
  414. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
  415. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
  416. /* mc_phyrstz field values */
  417. HDMI_MC_PHYRSTZ_ASSERT = 0x0,
  418. HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
  419. /* mc_heacphy_rst field values */
  420. HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
  421. /* i2cm filed values */
  422. HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
  423. HDMI_I2CM_SEGADDR_DDC = 0x30,
  424. HDMI_I2CM_OP_RD8_EXT = 0x2,
  425. HDMI_I2CM_OP_RD8 = 0x1,
  426. HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
  427. HDMI_I2CM_DIV_FAST_MODE = 0x8,
  428. HDMI_I2CM_DIV_STD_MODE = 0x0,
  429. HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
  430. /* CSC_CFG field values */
  431. HDMI_CSC_CFG_INTMODE_MASK = 0x30,
  432. HDMI_CSC_CFG_INTMODE_OFFSET = 4,
  433. HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
  434. HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
  435. HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
  436. HDMI_CSC_CFG_DECMODE_MASK = 0x3,
  437. HDMI_CSC_CFG_DECMODE_OFFSET = 0,
  438. HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
  439. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
  440. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
  441. HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
  442. /* CSC_SCALE field values */
  443. HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
  444. HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
  445. HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
  446. HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
  447. HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
  448. HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
  449. };
  450. struct hdmi_mpll_config {
  451. u64 mpixelclock;
  452. /* Mode of Operation and PLL Dividers Control Register */
  453. u32 cpce;
  454. /* PLL Gmp Control Register */
  455. u32 gmp;
  456. /* PLL Current Control Register */
  457. u32 curr;
  458. };
  459. struct hdmi_phy_config {
  460. u64 mpixelclock;
  461. u32 sym_ctr; /* clock symbol and transmitter control */
  462. u32 term; /* transmission termination value */
  463. u32 vlev_ctr; /* voltage level control */
  464. };
  465. struct hdmi_vmode {
  466. bool mdataenablepolarity;
  467. unsigned int mpixelclock;
  468. unsigned int mpixelrepetitioninput;
  469. unsigned int mpixelrepetitionoutput;
  470. };
  471. struct hdmi_data_info {
  472. unsigned int enc_in_bus_format;
  473. unsigned int enc_out_bus_format;
  474. unsigned int enc_in_encoding;
  475. unsigned int enc_out_encoding;
  476. unsigned int pix_repet_factor;
  477. unsigned int hdcp_enable;
  478. struct hdmi_vmode video_mode;
  479. };
  480. struct dw_hdmi {
  481. ulong ioaddr;
  482. const struct hdmi_mpll_config *mpll_cfg;
  483. const struct hdmi_phy_config *phy_cfg;
  484. u8 i2c_clk_high;
  485. u8 i2c_clk_low;
  486. u8 reg_io_width;
  487. struct hdmi_data_info hdmi_data;
  488. struct udevice *ddc_bus;
  489. int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
  490. void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset);
  491. u8 (*read_reg)(struct dw_hdmi *hdmi, int offset);
  492. };
  493. int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
  494. int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
  495. void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
  496. int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
  497. int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
  498. void dw_hdmi_init(struct dw_hdmi *hdmi);
  499. #endif