altr,rst-mgr-a10.h 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110
  1. /*
  2. * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
  14. #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
  15. /* MPUMODRST */
  16. #define CPU0_RESET 0
  17. #define CPU1_RESET 1
  18. #define WDS_RESET 2
  19. #define SCUPER_RESET 3
  20. /* PER0MODRST */
  21. #define EMAC0_RESET 32
  22. #define EMAC1_RESET 33
  23. #define EMAC2_RESET 34
  24. #define USB0_RESET 35
  25. #define USB1_RESET 36
  26. #define NAND_RESET 37
  27. #define QSPI_RESET 38
  28. #define SDMMC_RESET 39
  29. #define EMAC0_OCP_RESET 40
  30. #define EMAC1_OCP_RESET 41
  31. #define EMAC2_OCP_RESET 42
  32. #define USB0_OCP_RESET 43
  33. #define USB1_OCP_RESET 44
  34. #define NAND_OCP_RESET 45
  35. #define QSPI_OCP_RESET 46
  36. #define SDMMC_OCP_RESET 47
  37. #define DMA_RESET 48
  38. #define SPIM0_RESET 49
  39. #define SPIM1_RESET 50
  40. #define SPIS0_RESET 51
  41. #define SPIS1_RESET 52
  42. #define DMA_OCP_RESET 53
  43. #define EMAC_PTP_RESET 54
  44. /* 55 is empty*/
  45. #define DMAIF0_RESET 56
  46. #define DMAIF1_RESET 57
  47. #define DMAIF2_RESET 58
  48. #define DMAIF3_RESET 59
  49. #define DMAIF4_RESET 60
  50. #define DMAIF5_RESET 61
  51. #define DMAIF6_RESET 62
  52. #define DMAIF7_RESET 63
  53. /* PER1MODRST */
  54. #define L4WD0_RESET 64
  55. #define L4WD1_RESET 65
  56. #define L4SYSTIMER0_RESET 66
  57. #define L4SYSTIMER1_RESET 67
  58. #define SPTIMER0_RESET 68
  59. #define SPTIMER1_RESET 69
  60. /* 70-71 is reserved */
  61. #define I2C0_RESET 72
  62. #define I2C1_RESET 73
  63. #define I2C2_RESET 74
  64. #define I2C3_RESET 75
  65. #define I2C4_RESET 76
  66. /* 77-79 is reserved */
  67. #define UART0_RESET 80
  68. #define UART1_RESET 81
  69. /* 82-87 is reserved */
  70. #define GPIO0_RESET 88
  71. #define GPIO1_RESET 89
  72. #define GPIO2_RESET 90
  73. /* BRGMODRST */
  74. #define HPS2FPGA_RESET 96
  75. #define LWHPS2FPGA_RESET 97
  76. #define FPGA2HPS_RESET 98
  77. #define F2SSDRAM0_RESET 99
  78. #define F2SSDRAM1_RESET 100
  79. #define F2SSDRAM2_RESET 101
  80. #define DDRSCH_RESET 102
  81. /* SYSMODRST*/
  82. #define ROM_RESET 128
  83. #define OCRAM_RESET 129
  84. /* 130 is reserved */
  85. #define FPGAMGR_RESET 131
  86. #define S2F_RESET 132
  87. #define SYSDBG_RESET 133
  88. #define OCRAM_OCP_RESET 134
  89. /* COLDMODRST */
  90. #define CLKMGRCOLD_RESET 160
  91. /* 161-162 is reserved */
  92. #define S2FCOLD_RESET 163
  93. #define TIMESTAMPCOLD_RESET 164
  94. #define TAPCOLD_RESET 165
  95. #define HMCCOLD_RESET 166
  96. #define IOMGRCOLD_RESET 167
  97. /* NRSTMODRST */
  98. #define NRSTPINOE_RESET 192
  99. /* DBGMODRST */
  100. #define DBG_RESET 224
  101. #endif