pads-imx8qxp.h 75 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #ifndef _SC_PADS_H
  6. #define _SC_PADS_H
  7. #define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
  8. #define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
  9. #define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
  10. #define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */
  11. #define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
  12. #define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
  13. #define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
  14. #define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
  15. #define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */
  16. #define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
  17. #define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
  18. #define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
  19. #define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
  20. #define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
  21. #define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
  22. #define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /* */
  23. #define SC_P_EMMC0_DATA4 16 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
  24. #define SC_P_EMMC0_DATA5 17 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
  25. #define SC_P_EMMC0_DATA6 18 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
  26. #define SC_P_EMMC0_DATA7 19 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
  27. #define SC_P_EMMC0_STROBE 20 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
  28. #define SC_P_EMMC0_RESET_B 21 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
  29. #define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /* */
  30. #define SC_P_USDHC1_RESET_B 23 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
  31. #define SC_P_USDHC1_VSELECT 24 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
  32. #define SC_P_CTL_NAND_RE_P_N 25 /* */
  33. #define SC_P_USDHC1_WP 26 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
  34. #define SC_P_USDHC1_CD_B 27 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
  35. #define SC_P_CTL_NAND_DQS_P_N 28 /* */
  36. #define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /* */
  37. #define SC_P_USDHC1_CLK 30 /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
  38. #define SC_P_USDHC1_CMD 31 /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
  39. #define SC_P_USDHC1_DATA0 32 /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
  40. #define SC_P_USDHC1_DATA1 33 /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
  41. #define SC_P_USDHC1_DATA2 34 /* CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
  42. #define SC_P_USDHC1_DATA3 35 /* CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
  43. #define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /* */
  44. #define SC_P_ENET0_RGMII_TXC 37 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
  45. #define SC_P_ENET0_RGMII_TX_CTL 38 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
  46. #define SC_P_ENET0_RGMII_TXD0 39 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
  47. #define SC_P_ENET0_RGMII_TXD1 40 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
  48. #define SC_P_ENET0_RGMII_TXD2 41 /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
  49. #define SC_P_ENET0_RGMII_TXD3 42 /* CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
  50. #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /* */
  51. #define SC_P_ENET0_RGMII_RXC 44 /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
  52. #define SC_P_ENET0_RGMII_RX_CTL 45 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
  53. #define SC_P_ENET0_RGMII_RXD0 46 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
  54. #define SC_P_ENET0_RGMII_RXD1 47 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
  55. #define SC_P_ENET0_RGMII_RXD2 48 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
  56. #define SC_P_ENET0_RGMII_RXD3 49 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
  57. #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /* */
  58. #define SC_P_ENET0_REFCLK_125M_25M 51 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
  59. #define SC_P_ENET0_MDIO 52 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
  60. #define SC_P_ENET0_MDC 53 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
  61. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /* */
  62. #define SC_P_ESAI0_FSR 55 /* ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
  63. #define SC_P_ESAI0_FST 56 /* ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
  64. #define SC_P_ESAI0_SCKR 57 /* ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
  65. #define SC_P_ESAI0_SCKT 58 /* ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
  66. #define SC_P_ESAI0_TX0 59 /* ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
  67. #define SC_P_ESAI0_TX1 60 /* ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
  68. #define SC_P_ESAI0_TX2_RX3 61 /* ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
  69. #define SC_P_ESAI0_TX3_RX2 62 /* ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
  70. #define SC_P_ESAI0_TX4_RX1 63 /* ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
  71. #define SC_P_ESAI0_TX5_RX0 64 /* ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
  72. #define SC_P_SPDIF0_RX 65 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
  73. #define SC_P_SPDIF0_TX 66 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
  74. #define SC_P_SPDIF0_EXT_CLK 67 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
  75. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /* */
  76. #define SC_P_SPI3_SCK 69 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
  77. #define SC_P_SPI3_SDO 70 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
  78. #define SC_P_SPI3_SDI 71 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
  79. #define SC_P_SPI3_CS0 72 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
  80. #define SC_P_SPI3_CS1 73 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
  81. #define SC_P_MCLK_IN1 74 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
  82. #define SC_P_MCLK_IN0 75 /* ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
  83. #define SC_P_MCLK_OUT0 76 /* ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
  84. #define SC_P_UART1_TX 77 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
  85. #define SC_P_UART1_RX 78 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
  86. #define SC_P_UART1_RTS_B 79 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
  87. #define SC_P_UART1_CTS_B 80 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
  88. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /* */
  89. #define SC_P_SAI0_TXD 82 /* ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
  90. #define SC_P_SAI0_TXC 83 /* ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
  91. #define SC_P_SAI0_RXD 84 /* ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
  92. #define SC_P_SAI0_TXFS 85 /* ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
  93. #define SC_P_SAI1_RXD 86 /* ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
  94. #define SC_P_SAI1_RXC 87 /* ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
  95. #define SC_P_SAI1_RXFS 88 /* ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
  96. #define SC_P_SPI2_CS0 89 /* ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
  97. #define SC_P_SPI2_SDO 90 /* ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
  98. #define SC_P_SPI2_SDI 91 /* ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
  99. #define SC_P_SPI2_SCK 92 /* ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
  100. #define SC_P_SPI0_SCK 93 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
  101. #define SC_P_SPI0_SDI 94 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
  102. #define SC_P_SPI0_SDO 95 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
  103. #define SC_P_SPI0_CS1 96 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
  104. #define SC_P_SPI0_CS0 97 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
  105. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /* */
  106. #define SC_P_ADC_IN1 99 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
  107. #define SC_P_ADC_IN0 100 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
  108. #define SC_P_ADC_IN3 101 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
  109. #define SC_P_ADC_IN2 102 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
  110. #define SC_P_ADC_IN5 103 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
  111. #define SC_P_ADC_IN4 104 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
  112. #define SC_P_FLEXCAN0_RX 105 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
  113. #define SC_P_FLEXCAN0_TX 106 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
  114. #define SC_P_FLEXCAN1_RX 107 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
  115. #define SC_P_FLEXCAN1_TX 108 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
  116. #define SC_P_FLEXCAN2_RX 109 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
  117. #define SC_P_FLEXCAN2_TX 110 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
  118. #define SC_P_UART0_RX 111 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
  119. #define SC_P_UART0_TX 112 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
  120. #define SC_P_UART2_TX 113 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
  121. #define SC_P_UART2_RX 114 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
  122. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /* */
  123. #define SC_P_MIPI_DSI0_I2C0_SCL 116 /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
  124. #define SC_P_MIPI_DSI0_I2C0_SDA 117 /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
  125. #define SC_P_MIPI_DSI0_GPIO0_00 118 /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
  126. #define SC_P_MIPI_DSI0_GPIO0_01 119 /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
  127. #define SC_P_MIPI_DSI1_I2C0_SCL 120 /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
  128. #define SC_P_MIPI_DSI1_I2C0_SDA 121 /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
  129. #define SC_P_MIPI_DSI1_GPIO0_00 122 /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
  130. #define SC_P_MIPI_DSI1_GPIO0_01 123 /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
  131. #define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /* */
  132. #define SC_P_JTAG_TRST_B 125 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
  133. #define SC_P_PMIC_I2C_SCL 126 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
  134. #define SC_P_PMIC_I2C_SDA 127 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
  135. #define SC_P_PMIC_INT_B 128 /* SCU.DSC.PMIC_INT_B */
  136. #define SC_P_SCU_GPIO0_00 129 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
  137. #define SC_P_SCU_GPIO0_01 130 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
  138. #define SC_P_SCU_PMIC_STANDBY 131 /* SCU.DSC.PMIC_STANDBY */
  139. #define SC_P_SCU_BOOT_MODE0 132 /* SCU.DSC.BOOT_MODE0 */
  140. #define SC_P_SCU_BOOT_MODE1 133 /* SCU.DSC.BOOT_MODE1 */
  141. #define SC_P_SCU_BOOT_MODE2 134 /* SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
  142. #define SC_P_SCU_BOOT_MODE3 135 /* SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
  143. #define SC_P_CSI_D00 136 /* CI_PI.D02, ADMA.SAI0.RXC */
  144. #define SC_P_CSI_D01 137 /* CI_PI.D03, ADMA.SAI0.RXD */
  145. #define SC_P_CSI_D02 138 /* CI_PI.D04, ADMA.SAI0.RXFS */
  146. #define SC_P_CSI_D03 139 /* CI_PI.D05, ADMA.SAI2.RXC */
  147. #define SC_P_CSI_D04 140 /* CI_PI.D06, ADMA.SAI2.RXD */
  148. #define SC_P_CSI_D05 141 /* CI_PI.D07, ADMA.SAI2.RXFS */
  149. #define SC_P_CSI_D06 142 /* CI_PI.D08, ADMA.SAI3.RXC */
  150. #define SC_P_CSI_D07 143 /* CI_PI.D09, ADMA.SAI3.RXD */
  151. #define SC_P_CSI_HSYNC 144 /* CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
  152. #define SC_P_CSI_VSYNC 145 /* CI_PI.VSYNC, CI_PI.D01 */
  153. #define SC_P_CSI_PCLK 146 /* CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
  154. #define SC_P_CSI_MCLK 147 /* CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
  155. #define SC_P_CSI_EN 148 /* CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
  156. #define SC_P_CSI_RESET 149 /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
  157. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /* */
  158. #define SC_P_MIPI_CSI0_MCLK_OUT 151 /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
  159. #define SC_P_MIPI_CSI0_I2C0_SCL 152 /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
  160. #define SC_P_MIPI_CSI0_I2C0_SDA 153 /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
  161. #define SC_P_MIPI_CSI0_GPIO0_01 154 /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
  162. #define SC_P_MIPI_CSI0_GPIO0_00 155 /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
  163. #define SC_P_QSPI0A_DATA0 156 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
  164. #define SC_P_QSPI0A_DATA1 157 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
  165. #define SC_P_QSPI0A_DATA2 158 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
  166. #define SC_P_QSPI0A_DATA3 159 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
  167. #define SC_P_QSPI0A_DQS 160 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
  168. #define SC_P_QSPI0A_SS0_B 161 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
  169. #define SC_P_QSPI0A_SS1_B 162 /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
  170. #define SC_P_QSPI0A_SCLK 163 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
  171. #define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /* */
  172. #define SC_P_QSPI0B_SCLK 165 /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
  173. #define SC_P_QSPI0B_DATA0 166 /* LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
  174. #define SC_P_QSPI0B_DATA1 167 /* LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
  175. #define SC_P_QSPI0B_DATA2 168 /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
  176. #define SC_P_QSPI0B_DATA3 169 /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
  177. #define SC_P_QSPI0B_DQS 170 /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
  178. #define SC_P_QSPI0B_SS0_B 171 /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
  179. #define SC_P_QSPI0B_SS1_B 172 /* LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
  180. #define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /* */
  181. /*@}*/
  182. /*!
  183. * @name Pad Mux Definitions
  184. * format: name padid padmux
  185. */
  186. /*@{*/
  187. #define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0
  188. #define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4
  189. #define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0
  190. #define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4
  191. #define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0
  192. #define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4
  193. #define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0
  194. #define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1
  195. #define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2
  196. #define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4
  197. #define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0
  198. #define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1
  199. #define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4
  200. #define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0
  201. #define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1
  202. #define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2
  203. #define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4
  204. #define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0
  205. #define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1
  206. #define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4
  207. #define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0
  208. #define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1
  209. #define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4
  210. #define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0
  211. #define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1
  212. #define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4
  213. #define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0
  214. #define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1
  215. #define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4
  216. #define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0
  217. #define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1
  218. #define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4
  219. #define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0
  220. #define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1
  221. #define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4
  222. #define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0
  223. #define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1
  224. #define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4
  225. #define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0
  226. #define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1
  227. #define SC_P_EMMC0_DATA4_CONN_EMMC0_WP SC_P_EMMC0_DATA4 3
  228. #define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4
  229. #define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0
  230. #define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1
  231. #define SC_P_EMMC0_DATA5_CONN_EMMC0_VSELECT SC_P_EMMC0_DATA5 3
  232. #define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4
  233. #define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0
  234. #define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1
  235. #define SC_P_EMMC0_DATA6_CONN_MLB_CLK SC_P_EMMC0_DATA6 3
  236. #define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4
  237. #define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0
  238. #define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1
  239. #define SC_P_EMMC0_DATA7_CONN_MLB_SIG SC_P_EMMC0_DATA7 3
  240. #define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4
  241. #define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0
  242. #define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1
  243. #define SC_P_EMMC0_STROBE_CONN_MLB_DATA SC_P_EMMC0_STROBE 3
  244. #define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4
  245. #define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0
  246. #define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1
  247. #define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4
  248. #define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0
  249. #define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1
  250. #define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2
  251. #define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4
  252. #define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0
  253. #define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1
  254. #define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2
  255. #define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3
  256. #define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4
  257. #define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0
  258. #define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1
  259. #define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2
  260. #define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4
  261. #define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0
  262. #define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1
  263. #define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2
  264. #define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3
  265. #define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4
  266. #define SC_P_USDHC1_CLK_CONN_USDHC1_CLK SC_P_USDHC1_CLK 0
  267. #define SC_P_USDHC1_CLK_ADMA_UART3_RX SC_P_USDHC1_CLK 2
  268. #define SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 SC_P_USDHC1_CLK 4
  269. #define SC_P_USDHC1_CMD_CONN_USDHC1_CMD SC_P_USDHC1_CMD 0
  270. #define SC_P_USDHC1_CMD_CONN_NAND_CE0_B SC_P_USDHC1_CMD 1
  271. #define SC_P_USDHC1_CMD_ADMA_MQS_R SC_P_USDHC1_CMD 2
  272. #define SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 SC_P_USDHC1_CMD 4
  273. #define SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 SC_P_USDHC1_DATA0 0
  274. #define SC_P_USDHC1_DATA0_CONN_NAND_CE1_B SC_P_USDHC1_DATA0 1
  275. #define SC_P_USDHC1_DATA0_ADMA_MQS_L SC_P_USDHC1_DATA0 2
  276. #define SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 SC_P_USDHC1_DATA0 4
  277. #define SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 SC_P_USDHC1_DATA1 0
  278. #define SC_P_USDHC1_DATA1_CONN_NAND_RE_B SC_P_USDHC1_DATA1 1
  279. #define SC_P_USDHC1_DATA1_ADMA_UART3_TX SC_P_USDHC1_DATA1 2
  280. #define SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 SC_P_USDHC1_DATA1 4
  281. #define SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 SC_P_USDHC1_DATA2 0
  282. #define SC_P_USDHC1_DATA2_CONN_NAND_WE_B SC_P_USDHC1_DATA2 1
  283. #define SC_P_USDHC1_DATA2_ADMA_UART3_CTS_B SC_P_USDHC1_DATA2 2
  284. #define SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 SC_P_USDHC1_DATA2 4
  285. #define SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 SC_P_USDHC1_DATA3 0
  286. #define SC_P_USDHC1_DATA3_CONN_NAND_ALE SC_P_USDHC1_DATA3 1
  287. #define SC_P_USDHC1_DATA3_ADMA_UART3_RTS_B SC_P_USDHC1_DATA3 2
  288. #define SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 SC_P_USDHC1_DATA3 4
  289. #define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0
  290. #define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1
  291. #define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2
  292. #define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3
  293. #define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4
  294. #define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0
  295. #define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3
  296. #define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4
  297. #define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0
  298. #define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3
  299. #define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4
  300. #define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0
  301. #define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3
  302. #define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4
  303. #define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0
  304. #define SC_P_ENET0_RGMII_TXD2_CONN_MLB_CLK SC_P_ENET0_RGMII_TXD2 1
  305. #define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2
  306. #define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3
  307. #define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4
  308. #define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0
  309. #define SC_P_ENET0_RGMII_TXD3_CONN_MLB_SIG SC_P_ENET0_RGMII_TXD3 1
  310. #define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2
  311. #define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4
  312. #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
  313. #define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0
  314. #define SC_P_ENET0_RGMII_RXC_CONN_MLB_DATA SC_P_ENET0_RGMII_RXC 1
  315. #define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2
  316. #define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3
  317. #define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4
  318. #define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0
  319. #define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3
  320. #define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4
  321. #define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0
  322. #define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3
  323. #define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4
  324. #define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0
  325. #define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3
  326. #define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4
  327. #define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0
  328. #define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1
  329. #define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3
  330. #define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4
  331. #define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0
  332. #define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2
  333. #define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3
  334. #define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4
  335. #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
  336. #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0
  337. #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1
  338. #define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS SC_P_ENET0_REFCLK_125M_25M 2
  339. #define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4
  340. #define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0
  341. #define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1
  342. #define SC_P_ENET0_MDIO_CONN_ENET1_MDIO SC_P_ENET0_MDIO 2
  343. #define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4
  344. #define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0
  345. #define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1
  346. #define SC_P_ENET0_MDC_CONN_ENET1_MDC SC_P_ENET0_MDC 2
  347. #define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4
  348. #define SC_P_ESAI0_FSR_ADMA_ESAI0_FSR SC_P_ESAI0_FSR 0
  349. #define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT SC_P_ESAI0_FSR 1
  350. #define SC_P_ESAI0_FSR_ADMA_LCDIF_D00 SC_P_ESAI0_FSR 2
  351. #define SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC SC_P_ESAI0_FSR 3
  352. #define SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN SC_P_ESAI0_FSR 4
  353. #define SC_P_ESAI0_FST_ADMA_ESAI0_FST SC_P_ESAI0_FST 0
  354. #define SC_P_ESAI0_FST_CONN_MLB_CLK SC_P_ESAI0_FST 1
  355. #define SC_P_ESAI0_FST_ADMA_LCDIF_D01 SC_P_ESAI0_FST 2
  356. #define SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 SC_P_ESAI0_FST 3
  357. #define SC_P_ESAI0_FST_LSIO_GPIO0_IO01 SC_P_ESAI0_FST 4
  358. #define SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR SC_P_ESAI0_SCKR 0
  359. #define SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 SC_P_ESAI0_SCKR 2
  360. #define SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL SC_P_ESAI0_SCKR 3
  361. #define SC_P_ESAI0_SCKR_LSIO_GPIO0_IO02 SC_P_ESAI0_SCKR 4
  362. #define SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT SC_P_ESAI0_SCKT 0
  363. #define SC_P_ESAI0_SCKT_CONN_MLB_SIG SC_P_ESAI0_SCKT 1
  364. #define SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 SC_P_ESAI0_SCKT 2
  365. #define SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 SC_P_ESAI0_SCKT 3
  366. #define SC_P_ESAI0_SCKT_LSIO_GPIO0_IO03 SC_P_ESAI0_SCKT 4
  367. #define SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 SC_P_ESAI0_TX0 0
  368. #define SC_P_ESAI0_TX0_CONN_MLB_DATA SC_P_ESAI0_TX0 1
  369. #define SC_P_ESAI0_TX0_ADMA_LCDIF_D04 SC_P_ESAI0_TX0 2
  370. #define SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC SC_P_ESAI0_TX0 3
  371. #define SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 SC_P_ESAI0_TX0 4
  372. #define SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 SC_P_ESAI0_TX1 0
  373. #define SC_P_ESAI0_TX1_ADMA_LCDIF_D05 SC_P_ESAI0_TX1 2
  374. #define SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 SC_P_ESAI0_TX1 3
  375. #define SC_P_ESAI0_TX1_LSIO_GPIO0_IO05 SC_P_ESAI0_TX1 4
  376. #define SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 SC_P_ESAI0_TX2_RX3 0
  377. #define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER SC_P_ESAI0_TX2_RX3 1
  378. #define SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 SC_P_ESAI0_TX2_RX3 2
  379. #define SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 SC_P_ESAI0_TX2_RX3 3
  380. #define SC_P_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 SC_P_ESAI0_TX2_RX3 4
  381. #define SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 SC_P_ESAI0_TX3_RX2 0
  382. #define SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 SC_P_ESAI0_TX3_RX2 2
  383. #define SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 SC_P_ESAI0_TX3_RX2 3
  384. #define SC_P_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 SC_P_ESAI0_TX3_RX2 4
  385. #define SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 SC_P_ESAI0_TX4_RX1 0
  386. #define SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 SC_P_ESAI0_TX4_RX1 2
  387. #define SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 SC_P_ESAI0_TX4_RX1 3
  388. #define SC_P_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 SC_P_ESAI0_TX4_RX1 4
  389. #define SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 SC_P_ESAI0_TX5_RX0 0
  390. #define SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 SC_P_ESAI0_TX5_RX0 2
  391. #define SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 SC_P_ESAI0_TX5_RX0 3
  392. #define SC_P_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 SC_P_ESAI0_TX5_RX0 4
  393. #define SC_P_SPDIF0_RX_ADMA_SPDIF0_RX SC_P_SPDIF0_RX 0
  394. #define SC_P_SPDIF0_RX_ADMA_MQS_R SC_P_SPDIF0_RX 1
  395. #define SC_P_SPDIF0_RX_ADMA_LCDIF_D10 SC_P_SPDIF0_RX 2
  396. #define SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 SC_P_SPDIF0_RX 3
  397. #define SC_P_SPDIF0_RX_LSIO_GPIO0_IO10 SC_P_SPDIF0_RX 4
  398. #define SC_P_SPDIF0_TX_ADMA_SPDIF0_TX SC_P_SPDIF0_TX 0
  399. #define SC_P_SPDIF0_TX_ADMA_MQS_L SC_P_SPDIF0_TX 1
  400. #define SC_P_SPDIF0_TX_ADMA_LCDIF_D11 SC_P_SPDIF0_TX 2
  401. #define SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL SC_P_SPDIF0_TX 3
  402. #define SC_P_SPDIF0_TX_LSIO_GPIO0_IO11 SC_P_SPDIF0_TX 4
  403. #define SC_P_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK SC_P_SPDIF0_EXT_CLK 0
  404. #define SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 SC_P_SPDIF0_EXT_CLK 2
  405. #define SC_P_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M SC_P_SPDIF0_EXT_CLK 3
  406. #define SC_P_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 SC_P_SPDIF0_EXT_CLK 4
  407. #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
  408. #define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0
  409. #define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2
  410. #define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4
  411. #define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0
  412. #define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2
  413. #define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4
  414. #define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0
  415. #define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2
  416. #define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4
  417. #define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0
  418. #define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1
  419. #define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2
  420. #define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4
  421. #define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0
  422. #define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1
  423. #define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2
  424. #define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3
  425. #define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4
  426. #define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0
  427. #define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1
  428. #define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2
  429. #define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3
  430. #define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4
  431. #define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0
  432. #define SC_P_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK SC_P_MCLK_IN0 1
  433. #define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2
  434. #define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3
  435. #define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4
  436. #define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0
  437. #define SC_P_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK SC_P_MCLK_OUT0 1
  438. #define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2
  439. #define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3
  440. #define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4
  441. #define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0
  442. #define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1
  443. #define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2
  444. #define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4
  445. #define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0
  446. #define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1
  447. #define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2
  448. #define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3
  449. #define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4
  450. #define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0
  451. #define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1
  452. #define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2
  453. #define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3
  454. #define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4
  455. #define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0
  456. #define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1
  457. #define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2
  458. #define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3
  459. #define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4
  460. #define SC_P_SAI0_TXD_ADMA_SAI0_TXD SC_P_SAI0_TXD 0
  461. #define SC_P_SAI0_TXD_ADMA_SAI1_RXC SC_P_SAI0_TXD 1
  462. #define SC_P_SAI0_TXD_ADMA_SPI1_SDO SC_P_SAI0_TXD 2
  463. #define SC_P_SAI0_TXD_ADMA_LCDIF_D18 SC_P_SAI0_TXD 3
  464. #define SC_P_SAI0_TXD_LSIO_GPIO0_IO25 SC_P_SAI0_TXD 4
  465. #define SC_P_SAI0_TXC_ADMA_SAI0_TXC SC_P_SAI0_TXC 0
  466. #define SC_P_SAI0_TXC_ADMA_SAI1_TXD SC_P_SAI0_TXC 1
  467. #define SC_P_SAI0_TXC_ADMA_SPI1_SDI SC_P_SAI0_TXC 2
  468. #define SC_P_SAI0_TXC_ADMA_LCDIF_D19 SC_P_SAI0_TXC 3
  469. #define SC_P_SAI0_TXC_LSIO_GPIO0_IO26 SC_P_SAI0_TXC 4
  470. #define SC_P_SAI0_RXD_ADMA_SAI0_RXD SC_P_SAI0_RXD 0
  471. #define SC_P_SAI0_RXD_ADMA_SAI1_RXFS SC_P_SAI0_RXD 1
  472. #define SC_P_SAI0_RXD_ADMA_SPI1_CS0 SC_P_SAI0_RXD 2
  473. #define SC_P_SAI0_RXD_ADMA_LCDIF_D20 SC_P_SAI0_RXD 3
  474. #define SC_P_SAI0_RXD_LSIO_GPIO0_IO27 SC_P_SAI0_RXD 4
  475. #define SC_P_SAI0_TXFS_ADMA_SAI0_TXFS SC_P_SAI0_TXFS 0
  476. #define SC_P_SAI0_TXFS_ADMA_SPI2_CS1 SC_P_SAI0_TXFS 1
  477. #define SC_P_SAI0_TXFS_ADMA_SPI1_SCK SC_P_SAI0_TXFS 2
  478. #define SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 SC_P_SAI0_TXFS 4
  479. #define SC_P_SAI1_RXD_ADMA_SAI1_RXD SC_P_SAI1_RXD 0
  480. #define SC_P_SAI1_RXD_ADMA_SAI0_RXFS SC_P_SAI1_RXD 1
  481. #define SC_P_SAI1_RXD_ADMA_SPI1_CS1 SC_P_SAI1_RXD 2
  482. #define SC_P_SAI1_RXD_ADMA_LCDIF_D21 SC_P_SAI1_RXD 3
  483. #define SC_P_SAI1_RXD_LSIO_GPIO0_IO29 SC_P_SAI1_RXD 4
  484. #define SC_P_SAI1_RXC_ADMA_SAI1_RXC SC_P_SAI1_RXC 0
  485. #define SC_P_SAI1_RXC_ADMA_SAI1_TXC SC_P_SAI1_RXC 1
  486. #define SC_P_SAI1_RXC_ADMA_LCDIF_D22 SC_P_SAI1_RXC 3
  487. #define SC_P_SAI1_RXC_LSIO_GPIO0_IO30 SC_P_SAI1_RXC 4
  488. #define SC_P_SAI1_RXFS_ADMA_SAI1_RXFS SC_P_SAI1_RXFS 0
  489. #define SC_P_SAI1_RXFS_ADMA_SAI1_TXFS SC_P_SAI1_RXFS 1
  490. #define SC_P_SAI1_RXFS_ADMA_LCDIF_D23 SC_P_SAI1_RXFS 3
  491. #define SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 SC_P_SAI1_RXFS 4
  492. #define SC_P_SPI2_CS0_ADMA_SPI2_CS0 SC_P_SPI2_CS0 0
  493. #define SC_P_SPI2_CS0_LSIO_GPIO1_IO00 SC_P_SPI2_CS0 4
  494. #define SC_P_SPI2_SDO_ADMA_SPI2_SDO SC_P_SPI2_SDO 0
  495. #define SC_P_SPI2_SDO_LSIO_GPIO1_IO01 SC_P_SPI2_SDO 4
  496. #define SC_P_SPI2_SDI_ADMA_SPI2_SDI SC_P_SPI2_SDI 0
  497. #define SC_P_SPI2_SDI_LSIO_GPIO1_IO02 SC_P_SPI2_SDI 4
  498. #define SC_P_SPI2_SCK_ADMA_SPI2_SCK SC_P_SPI2_SCK 0
  499. #define SC_P_SPI2_SCK_LSIO_GPIO1_IO03 SC_P_SPI2_SCK 4
  500. #define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0
  501. #define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1
  502. #define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2
  503. #define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3
  504. #define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4
  505. #define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0
  506. #define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1
  507. #define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2
  508. #define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3
  509. #define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4
  510. #define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0
  511. #define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1
  512. #define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2
  513. #define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3
  514. #define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4
  515. #define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0
  516. #define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1
  517. #define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2
  518. #define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3
  519. #define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4
  520. #define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0
  521. #define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1
  522. #define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2
  523. #define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3
  524. #define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4
  525. #define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0
  526. #define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1
  527. #define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2
  528. #define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4
  529. #define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0
  530. #define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1
  531. #define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2
  532. #define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4
  533. #define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0
  534. #define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1
  535. #define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2
  536. #define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3
  537. #define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4
  538. #define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0
  539. #define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1
  540. #define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2
  541. #define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3
  542. #define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4
  543. #define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0
  544. #define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1
  545. #define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2
  546. #define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4
  547. #define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0
  548. #define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1
  549. #define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2
  550. #define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4
  551. #define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0
  552. #define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1
  553. #define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2
  554. #define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3
  555. #define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4
  556. #define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0
  557. #define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1
  558. #define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2
  559. #define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3
  560. #define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4
  561. #define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0
  562. #define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1
  563. #define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2
  564. #define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3
  565. #define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4
  566. #define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0
  567. #define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1
  568. #define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2
  569. #define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3
  570. #define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4
  571. #define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0
  572. #define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1
  573. #define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2
  574. #define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3
  575. #define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4
  576. #define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0
  577. #define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1
  578. #define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2
  579. #define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3
  580. #define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4
  581. #define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0
  582. #define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1
  583. #define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2
  584. #define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3
  585. #define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4
  586. #define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0
  587. #define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1
  588. #define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2
  589. #define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3
  590. #define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4
  591. #define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0
  592. #define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1
  593. #define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2
  594. #define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4
  595. #define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0
  596. #define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1
  597. #define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2
  598. #define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4
  599. #define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL SC_P_MIPI_DSI0_I2C0_SCL 0
  600. #define SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 SC_P_MIPI_DSI0_I2C0_SCL 1
  601. #define SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 SC_P_MIPI_DSI0_I2C0_SCL 4
  602. #define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA SC_P_MIPI_DSI0_I2C0_SDA 0
  603. #define SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 SC_P_MIPI_DSI0_I2C0_SDA 1
  604. #define SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 SC_P_MIPI_DSI0_I2C0_SDA 4
  605. #define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 SC_P_MIPI_DSI0_GPIO0_00 0
  606. #define SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL SC_P_MIPI_DSI0_GPIO0_00 1
  607. #define SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT SC_P_MIPI_DSI0_GPIO0_00 2
  608. #define SC_P_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 SC_P_MIPI_DSI0_GPIO0_00 4
  609. #define SC_P_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 SC_P_MIPI_DSI0_GPIO0_01 0
  610. #define SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA SC_P_MIPI_DSI0_GPIO0_01 1
  611. #define SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 SC_P_MIPI_DSI0_GPIO0_01 4
  612. #define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL SC_P_MIPI_DSI1_I2C0_SCL 0
  613. #define SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 SC_P_MIPI_DSI1_I2C0_SCL 1
  614. #define SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 SC_P_MIPI_DSI1_I2C0_SCL 4
  615. #define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA SC_P_MIPI_DSI1_I2C0_SDA 0
  616. #define SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 SC_P_MIPI_DSI1_I2C0_SDA 1
  617. #define SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 SC_P_MIPI_DSI1_I2C0_SDA 4
  618. #define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 SC_P_MIPI_DSI1_GPIO0_00 0
  619. #define SC_P_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL SC_P_MIPI_DSI1_GPIO0_00 1
  620. #define SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT SC_P_MIPI_DSI1_GPIO0_00 2
  621. #define SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 SC_P_MIPI_DSI1_GPIO0_00 4
  622. #define SC_P_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 SC_P_MIPI_DSI1_GPIO0_01 0
  623. #define SC_P_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA SC_P_MIPI_DSI1_GPIO0_01 1
  624. #define SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 SC_P_MIPI_DSI1_GPIO0_01 4
  625. #define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0
  626. #define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1
  627. #define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0
  628. #define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1
  629. #define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4
  630. #define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0
  631. #define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1
  632. #define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4
  633. #define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0
  634. #define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0
  635. #define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1
  636. #define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2
  637. #define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3
  638. #define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4
  639. #define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0
  640. #define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1
  641. #define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2
  642. #define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3
  643. #define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4
  644. #define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0
  645. #define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0
  646. #define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0
  647. #define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0
  648. #define SC_P_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA SC_P_SCU_BOOT_MODE2 1
  649. #define SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 SC_P_SCU_BOOT_MODE3 0
  650. #define SC_P_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL SC_P_SCU_BOOT_MODE3 1
  651. #define SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE3 3
  652. #define SC_P_CSI_D00_CI_PI_D02 SC_P_CSI_D00 0
  653. #define SC_P_CSI_D00_ADMA_SAI0_RXC SC_P_CSI_D00 2
  654. #define SC_P_CSI_D01_CI_PI_D03 SC_P_CSI_D01 0
  655. #define SC_P_CSI_D01_ADMA_SAI0_RXD SC_P_CSI_D01 2
  656. #define SC_P_CSI_D02_CI_PI_D04 SC_P_CSI_D02 0
  657. #define SC_P_CSI_D02_ADMA_SAI0_RXFS SC_P_CSI_D02 2
  658. #define SC_P_CSI_D03_CI_PI_D05 SC_P_CSI_D03 0
  659. #define SC_P_CSI_D03_ADMA_SAI2_RXC SC_P_CSI_D03 2
  660. #define SC_P_CSI_D04_CI_PI_D06 SC_P_CSI_D04 0
  661. #define SC_P_CSI_D04_ADMA_SAI2_RXD SC_P_CSI_D04 2
  662. #define SC_P_CSI_D05_CI_PI_D07 SC_P_CSI_D05 0
  663. #define SC_P_CSI_D05_ADMA_SAI2_RXFS SC_P_CSI_D05 2
  664. #define SC_P_CSI_D06_CI_PI_D08 SC_P_CSI_D06 0
  665. #define SC_P_CSI_D06_ADMA_SAI3_RXC SC_P_CSI_D06 2
  666. #define SC_P_CSI_D07_CI_PI_D09 SC_P_CSI_D07 0
  667. #define SC_P_CSI_D07_ADMA_SAI3_RXD SC_P_CSI_D07 2
  668. #define SC_P_CSI_HSYNC_CI_PI_HSYNC SC_P_CSI_HSYNC 0
  669. #define SC_P_CSI_HSYNC_CI_PI_D00 SC_P_CSI_HSYNC 1
  670. #define SC_P_CSI_HSYNC_ADMA_SAI3_RXFS SC_P_CSI_HSYNC 2
  671. #define SC_P_CSI_VSYNC_CI_PI_VSYNC SC_P_CSI_VSYNC 0
  672. #define SC_P_CSI_VSYNC_CI_PI_D01 SC_P_CSI_VSYNC 1
  673. #define SC_P_CSI_PCLK_CI_PI_PCLK SC_P_CSI_PCLK 0
  674. #define SC_P_CSI_PCLK_MIPI_CSI0_I2C0_SCL SC_P_CSI_PCLK 1
  675. #define SC_P_CSI_PCLK_ADMA_SPI1_SCK SC_P_CSI_PCLK 3
  676. #define SC_P_CSI_PCLK_LSIO_GPIO3_IO00 SC_P_CSI_PCLK 4
  677. #define SC_P_CSI_MCLK_CI_PI_MCLK SC_P_CSI_MCLK 0
  678. #define SC_P_CSI_MCLK_MIPI_CSI0_I2C0_SDA SC_P_CSI_MCLK 1
  679. #define SC_P_CSI_MCLK_ADMA_SPI1_SDO SC_P_CSI_MCLK 3
  680. #define SC_P_CSI_MCLK_LSIO_GPIO3_IO01 SC_P_CSI_MCLK 4
  681. #define SC_P_CSI_EN_CI_PI_EN SC_P_CSI_EN 0
  682. #define SC_P_CSI_EN_CI_PI_I2C_SCL SC_P_CSI_EN 1
  683. #define SC_P_CSI_EN_ADMA_I2C3_SCL SC_P_CSI_EN 2
  684. #define SC_P_CSI_EN_ADMA_SPI1_SDI SC_P_CSI_EN 3
  685. #define SC_P_CSI_EN_LSIO_GPIO3_IO02 SC_P_CSI_EN 4
  686. #define SC_P_CSI_RESET_CI_PI_RESET SC_P_CSI_RESET 0
  687. #define SC_P_CSI_RESET_CI_PI_I2C_SDA SC_P_CSI_RESET 1
  688. #define SC_P_CSI_RESET_ADMA_I2C3_SDA SC_P_CSI_RESET 2
  689. #define SC_P_CSI_RESET_ADMA_SPI1_CS0 SC_P_CSI_RESET 3
  690. #define SC_P_CSI_RESET_LSIO_GPIO3_IO03 SC_P_CSI_RESET 4
  691. #define SC_P_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT SC_P_MIPI_CSI0_MCLK_OUT 0
  692. #define SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 SC_P_MIPI_CSI0_MCLK_OUT 4
  693. #define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL SC_P_MIPI_CSI0_I2C0_SCL 0
  694. #define SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 SC_P_MIPI_CSI0_I2C0_SCL 1
  695. #define SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 SC_P_MIPI_CSI0_I2C0_SCL 4
  696. #define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA SC_P_MIPI_CSI0_I2C0_SDA 0
  697. #define SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 SC_P_MIPI_CSI0_I2C0_SDA 1
  698. #define SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 SC_P_MIPI_CSI0_I2C0_SDA 4
  699. #define SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 SC_P_MIPI_CSI0_GPIO0_01 0
  700. #define SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA SC_P_MIPI_CSI0_GPIO0_01 1
  701. #define SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 SC_P_MIPI_CSI0_GPIO0_01 4
  702. #define SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 SC_P_MIPI_CSI0_GPIO0_00 0
  703. #define SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL SC_P_MIPI_CSI0_GPIO0_00 1
  704. #define SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 SC_P_MIPI_CSI0_GPIO0_00 4
  705. #define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0
  706. #define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4
  707. #define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0
  708. #define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4
  709. #define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0
  710. #define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4
  711. #define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0
  712. #define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4
  713. #define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0
  714. #define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4
  715. #define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0
  716. #define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4
  717. #define SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0A_SS1_B 0
  718. #define SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 SC_P_QSPI0A_SS1_B 4
  719. #define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0
  720. #define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4
  721. #define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0
  722. #define SC_P_QSPI0B_SCLK_LSIO_QSPI1A_SCLK SC_P_QSPI0B_SCLK 1
  723. #define SC_P_QSPI0B_SCLK_LSIO_KPP0_COL0 SC_P_QSPI0B_SCLK 2
  724. #define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4
  725. #define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0
  726. #define SC_P_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 SC_P_QSPI0B_DATA0 1
  727. #define SC_P_QSPI0B_DATA0_LSIO_KPP0_COL1 SC_P_QSPI0B_DATA0 2
  728. #define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4
  729. #define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0
  730. #define SC_P_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 SC_P_QSPI0B_DATA1 1
  731. #define SC_P_QSPI0B_DATA1_LSIO_KPP0_COL2 SC_P_QSPI0B_DATA1 2
  732. #define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4
  733. #define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0
  734. #define SC_P_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 SC_P_QSPI0B_DATA2 1
  735. #define SC_P_QSPI0B_DATA2_LSIO_KPP0_COL3 SC_P_QSPI0B_DATA2 2
  736. #define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4
  737. #define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0
  738. #define SC_P_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 SC_P_QSPI0B_DATA3 1
  739. #define SC_P_QSPI0B_DATA3_LSIO_KPP0_ROW0 SC_P_QSPI0B_DATA3 2
  740. #define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4
  741. #define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0
  742. #define SC_P_QSPI0B_DQS_LSIO_QSPI1A_DQS SC_P_QSPI0B_DQS 1
  743. #define SC_P_QSPI0B_DQS_LSIO_KPP0_ROW1 SC_P_QSPI0B_DQS 2
  744. #define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4
  745. #define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0
  746. #define SC_P_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B SC_P_QSPI0B_SS0_B 1
  747. #define SC_P_QSPI0B_SS0_B_LSIO_KPP0_ROW2 SC_P_QSPI0B_SS0_B 2
  748. #define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4
  749. #define SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B SC_P_QSPI0B_SS1_B 0
  750. #define SC_P_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B SC_P_QSPI0B_SS1_B 1
  751. #define SC_P_QSPI0B_SS1_B_LSIO_KPP0_ROW3 SC_P_QSPI0B_SS1_B 2
  752. #define SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 SC_P_QSPI0B_SS1_B 4
  753. #endif /* _SC_PADS_H */