mpc83xx-sdram.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #ifndef DT_BINDINGS_MPC83XX_SDRAM_H
  7. #define DT_BINDINGS_MPC83XX_SDRAM_H
  8. /* DDR Control Driver register */
  9. #define DSO_DISABLE 0
  10. #define DSO_ENABLE 1
  11. #define DSO_P_IMPEDANCE_HIGHEST_Z 0x0
  12. #define DSO_P_IMPEDANCE_MUCH_HIGHER_Z 0x8
  13. #define DSO_P_IMPEDANCE_HIGHER_Z 0xC
  14. #define DSO_P_IMPEDANCE_NOMINAL 0xE
  15. #define DSO_P_IMPEDANCE_LOWER_Z 0xF
  16. #define DSO_N_IMPEDANCE_HIGHEST_Z 0x0
  17. #define DSO_N_IMPEDANCE_MUCH_HIGHER_Z 0x8
  18. #define DSO_N_IMPEDANCE_HIGHER_Z 0xC
  19. #define DSO_N_IMPEDANCE_NOMINAL 0xE
  20. #define DSO_N_IMPEDANCE_LOWER_Z 0xF
  21. #define ODT_TERMINATION_75_OHM 0
  22. #define ODT_TERMINATION_150_OHM 1
  23. #define DDR_TYPE_DDR2_1_8_VOLT 0
  24. #define DDR_TYPE_DDR1_2_5_VOLT 1
  25. #define MVREF_SEL_EXTERNAL 0
  26. #define MVREF_SEL_INTERNAL_GVDD 1
  27. #define M_ODR_ENABLE 0
  28. #define M_ODR_DISABLE 1
  29. /* CS config register */
  30. #define AUTO_PRECHARGE_ENABLE 0x00800000
  31. #define AUTO_PRECHARGE_DISABLE 0x00000000
  32. #define ODT_RD_NEVER 0x00000000
  33. #define ODT_RD_ONLY_CURRENT 0x00100000
  34. #define ODT_RD_ONLY_OTHER_CS 0x00200000
  35. #define ODT_RD_ONLY_OTHER_DIMM 0x00300000
  36. #define ODT_RD_ALL 0x00400000
  37. #define ODT_WR_NEVER 0x00000000
  38. #define ODT_WR_ONLY_CURRENT 0x00010000
  39. #define ODT_WR_ONLY_OTHER_CS 0x00020000
  40. #define ODT_WR_ONLY_OTHER_DIMM 0x00030000
  41. #define ODT_WR_ALL 0x00040000
  42. /* DDR SDRAM Clock Control register */
  43. #define CLOCK_ADJUST_025 0x01000000
  44. #define CLOCK_ADJUST_05 0x02000000
  45. #define CLOCK_ADJUST_075 0x03000000
  46. #define CLOCK_ADJUST_1 0x04000000
  47. #define CASLAT_20 0x3 /* CAS latency = 2.0 */
  48. #define CASLAT_25 0x4 /* CAS latency = 2.5 */
  49. #define CASLAT_30 0x5 /* CAS latency = 3.0 */
  50. #define CASLAT_35 0x6 /* CAS latency = 3.5 */
  51. #define CASLAT_40 0x7 /* CAS latency = 4.0 */
  52. #define CASLAT_45 0x8 /* CAS latency = 4.5 */
  53. #define CASLAT_50 0x9 /* CAS latency = 5.0 */
  54. #define CASLAT_55 0xa /* CAS latency = 5.5 */
  55. #define CASLAT_60 0xb /* CAS latency = 6.0 */
  56. #define CASLAT_65 0xc /* CAS latency = 6.5 */
  57. #define CASLAT_70 0xd /* CAS latency = 7.0 */
  58. #define CASLAT_75 0xe /* CAS latency = 7.5 */
  59. #define CASLAT_80 0xf /* CAS latency = 8.0 */
  60. /* DDR SDRAM Timing Configuration 2 register */
  61. #define READ_LAT_PLUS_1 0x0
  62. #define READ_LAT 0x2
  63. #define READ_LAT_PLUS_1_4 0x3
  64. #define READ_LAT_PLUS_1_2 0x4
  65. #define READ_LAT_PLUS_3_4 0x5
  66. #define READ_LAT_PLUS_5_4 0x7
  67. #define READ_LAT_PLUS_3_2 0x8
  68. #define READ_LAT_PLUS_7_4 0x9
  69. #define READ_LAT_PLUS_2 0xA
  70. #define READ_LAT_PLUS_9_4 0xB
  71. #define READ_LAT_PLUS_5_2 0xC
  72. #define READ_LAT_PLUS_11_4 0xD
  73. #define READ_LAT_PLUS_3 0xE
  74. #define READ_LAT_PLUS_13_4 0xF
  75. #define READ_LAT_PLUS_7_2 0x10
  76. #define READ_LAT_PLUS_15_4 0x11
  77. #define READ_LAT_PLUS_4 0x12
  78. #define READ_LAT_PLUS_17_4 0x13
  79. #define READ_LAT_PLUS_9_2 0x14
  80. #define READ_LAT_PLUS_19_4 0x15
  81. #define CLOCK_DELAY_0 0x0
  82. #define CLOCK_DELAY_1_4 0x1
  83. #define CLOCK_DELAY_1_2 0x2
  84. #define CLOCK_DELAY_3_4 0x3
  85. #define CLOCK_DELAY_1 0x4
  86. #define CLOCK_DELAY_5_4 0x5
  87. #define CLOCK_DELAY_3_2 0x6
  88. /* DDR SDRAM Control Configuration */
  89. #define SREN_DISABLE 0x0
  90. #define SREN_ENABLE 0x1
  91. #define ECC_DISABLE 0x0
  92. #define ECC_ENABLE 0x1
  93. #define RD_DISABLE 0x0
  94. #define RD_ENABLE 0x1
  95. #define TYPE_DDR1 0x2
  96. #define TYPE_DDR2 0x3
  97. #define DYN_PWR_DISABLE 0x0
  98. #define DYN_PWR_ENABLE 0x1
  99. #define DATA_BUS_WIDTH_16 0x1
  100. #define DATA_BUS_WIDTH_32 0x2
  101. #define NCAP_DISABLE 0x0
  102. #define NCAP_ENABLE 0x1
  103. #define TIMING_1T 0x0
  104. #define TIMING_2T 0x1
  105. #define INTERLEAVE_NONE 0x0
  106. #define INTERLEAVE_1_AND_2 0x1
  107. #define PRECHARGE_MA_10 0x0
  108. #define PRECHARGE_MA_8 0x1
  109. #define STRENGTH_FULL 0x0
  110. #define STRENGTH_HALF 0x1
  111. #define INITIALIZATION_DONT_BYPASS 0x0
  112. #define INITIALIZATION_BYPASS 0x1
  113. /* DDR SDRAM Control Configuration 2 register */
  114. #define MODE_NORMAL 0x0
  115. #define MODE_REFRESH 0x1
  116. #define DLL_RESET_ENABLE 0x0
  117. #define DLL_RESET_DISABLE 0x1
  118. #define DQS_TRUE 0x0
  119. #define ODT_ASSERT_NEVER 0x0
  120. #define ODT_ASSERT_WRITES 0x1
  121. #define ODT_ASSERT_READS 0x2
  122. #define ODT_ASSERT_ALWAYS 0x3
  123. #endif