imxrt-sdram.h 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2019
  4. * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
  5. */
  6. #ifndef DT_BINDINGS_IMXRT_SDRAM_H
  7. #define DT_BINDINGS_IMXRT_SDRAM_H
  8. #define MEM_SIZE_4K 0x00
  9. #define MEM_SIZE_8K 0x01
  10. #define MEM_SIZE_16K 0x02
  11. #define MEM_SIZE_32K 0x03
  12. #define MEM_SIZE_64K 0x04
  13. #define MEM_SIZE_128K 0x05
  14. #define MEM_SIZE_256K 0x06
  15. #define MEM_SIZE_512K 0x07
  16. #define MEM_SIZE_1M 0x08
  17. #define MEM_SIZE_2M 0x09
  18. #define MEM_SIZE_4M 0x0A
  19. #define MEM_SIZE_8M 0x0B
  20. #define MEM_SIZE_16M 0x0C
  21. #define MEM_SIZE_32M 0x0D
  22. #define MEM_SIZE_64M 0x0E
  23. #define MEM_SIZE_128M 0x0F
  24. #define MEM_SIZE_256M 0x10
  25. #define MEM_SIZE_512M 0x11
  26. #define MEM_SIZE_1G 0x12
  27. #define MEM_SIZE_2G 0x13
  28. #define MEM_SIZE_4G 0x14
  29. #define MUX_A8_SDRAM_A8 0x0
  30. #define MUX_A8_NAND_CE 0x1
  31. #define MUX_A8_NOR_CE 0x2
  32. #define MUX_A8_PSRAM_CE 0x3
  33. #define MUX_A8_DBI_CSX 0x4
  34. #define MUX_CSX0_NOR_PSRAM_A24 0x0
  35. #define MUX_CSX0_SDRAM_CS1 0x1
  36. #define MUX_CSX0_SDRAM_CS2 0x2
  37. #define MUX_CSX0_SDRAM_CS3 0x3
  38. #define MUX_CSX0_NAND_CE 0x4
  39. #define MUX_CSX0_NOR_CE 0x5
  40. #define MUX_CSX0_PSRAM_CE 0x6
  41. #define MUX_CSX0_DBI_CSX 0x7
  42. #define MUX_CSX1_NOR_PSRAM_A25 0x0
  43. #define MUX_CSX1_SDRAM_CS1 0x1
  44. #define MUX_CSX1_SDRAM_CS2 0x2
  45. #define MUX_CSX1_SDRAM_CS3 0x3
  46. #define MUX_CSX1_NAND_CE 0x4
  47. #define MUX_CSX1_NOR_CE 0x5
  48. #define MUX_CSX1_PSRAM_CE 0x6
  49. #define MUX_CSX1_DBI_CSX 0x7
  50. #define MUX_CSX2_NOR_PSRAM_A26 0x0
  51. #define MUX_CSX2_SDRAM_CS1 0x1
  52. #define MUX_CSX2_SDRAM_CS2 0x2
  53. #define MUX_CSX2_SDRAM_CS3 0x3
  54. #define MUX_CSX2_NAND_CE 0x4
  55. #define MUX_CSX2_NOR_CE 0x5
  56. #define MUX_CSX2_PSRAM_CE 0x6
  57. #define MUX_CSX2_DBI_CSX 0x7
  58. #define MUX_CSX3_NOR_PSRAM_A27 0x0
  59. #define MUX_CSX3_SDRAM_CS1 0x1
  60. #define MUX_CSX3_SDRAM_CS2 0x2
  61. #define MUX_CSX3_SDRAM_CS3 0x3
  62. #define MUX_CSX3_NAND_CE 0x4
  63. #define MUX_CSX3_NOR_CE 0x5
  64. #define MUX_CSX3_PSRAM_CE 0x6
  65. #define MUX_CSX3_DBI_CSX 0x7
  66. #define MUX_RDY_NAND_RDY_WAIT 0x0
  67. #define MUX_RDY_SDRAM_CS1 0x1
  68. #define MUX_RDY_SDRAM_CS2 0x2
  69. #define MUX_RDY_SDRAM_CS3 0x3
  70. #define MUX_RDY_NOR_CE 0x4
  71. #define MUX_RDY_PSRAM_CE 0x5
  72. #define MUX_RDY_DBI_CSX 0x6
  73. #define MUX_RDY_NOR_PSRAM_A27 0x7
  74. #define MEM_WIDTH_8BITS 0x0
  75. #define MEM_WIDTH_16BITS 0x1
  76. #define BL_1 0x0
  77. #define BL_2 0x1
  78. #define BL_4 0x2
  79. #define BL_8 0x3
  80. #define COL_12BITS 0x0
  81. #define COL_11BITS 0x1
  82. #define COL_10BITS 0x2
  83. #define COL_9BITS 0x3
  84. #define CL_1 0x0
  85. #define CL_2 0x2
  86. #define CL_3 0x3
  87. #endif