tegra186-clock.h 40 KB

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  1. /** @file */
  2. #ifndef _MACH_T186_CLK_T186_H
  3. #define _MACH_T186_CLK_T186_H
  4. /**
  5. * @defgroup clock_ids Clock Identifiers
  6. * @{
  7. * @defgroup extern_input external input clocks
  8. * @{
  9. * @def TEGRA186_CLK_OSC
  10. * @def TEGRA186_CLK_CLK_32K
  11. * @def TEGRA186_CLK_DTV_INPUT
  12. * @def TEGRA186_CLK_SOR0_PAD_CLKOUT
  13. * @def TEGRA186_CLK_SOR1_PAD_CLKOUT
  14. * @def TEGRA186_CLK_I2S1_SYNC_INPUT
  15. * @def TEGRA186_CLK_I2S2_SYNC_INPUT
  16. * @def TEGRA186_CLK_I2S3_SYNC_INPUT
  17. * @def TEGRA186_CLK_I2S4_SYNC_INPUT
  18. * @def TEGRA186_CLK_I2S5_SYNC_INPUT
  19. * @def TEGRA186_CLK_I2S6_SYNC_INPUT
  20. * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
  21. * @}
  22. *
  23. * @defgroup extern_output external output clocks
  24. * @{
  25. * @def TEGRA186_CLK_EXTPERIPH1
  26. * @def TEGRA186_CLK_EXTPERIPH2
  27. * @def TEGRA186_CLK_EXTPERIPH3
  28. * @def TEGRA186_CLK_EXTPERIPH4
  29. * @}
  30. *
  31. * @defgroup display_clks display related clocks
  32. * @{
  33. * @def TEGRA186_CLK_CEC
  34. * @def TEGRA186_CLK_DSIC
  35. * @def TEGRA186_CLK_DSIC_LP
  36. * @def TEGRA186_CLK_DSID
  37. * @def TEGRA186_CLK_DSID_LP
  38. * @def TEGRA186_CLK_DPAUX1
  39. * @def TEGRA186_CLK_DPAUX
  40. * @def TEGRA186_CLK_HDA2HDMICODEC
  41. * @def TEGRA186_CLK_NVDISPLAY_DISP
  42. * @def TEGRA186_CLK_NVDISPLAY_DSC
  43. * @def TEGRA186_CLK_NVDISPLAY_P0
  44. * @def TEGRA186_CLK_NVDISPLAY_P1
  45. * @def TEGRA186_CLK_NVDISPLAY_P2
  46. * @def TEGRA186_CLK_NVDISPLAYHUB
  47. * @def TEGRA186_CLK_SOR_SAFE
  48. * @def TEGRA186_CLK_SOR0
  49. * @def TEGRA186_CLK_SOR0_OUT
  50. * @def TEGRA186_CLK_SOR1
  51. * @def TEGRA186_CLK_SOR1_OUT
  52. * @def TEGRA186_CLK_DSI
  53. * @def TEGRA186_CLK_MIPI_CAL
  54. * @def TEGRA186_CLK_DSIA_LP
  55. * @def TEGRA186_CLK_DSIB
  56. * @def TEGRA186_CLK_DSIB_LP
  57. * @}
  58. *
  59. * @defgroup camera_clks camera related clocks
  60. * @{
  61. * @def TEGRA186_CLK_NVCSI
  62. * @def TEGRA186_CLK_NVCSILP
  63. * @def TEGRA186_CLK_VI
  64. * @}
  65. *
  66. * @defgroup audio_clks audio related clocks
  67. * @{
  68. * @def TEGRA186_CLK_ACLK
  69. * @def TEGRA186_CLK_ADSP
  70. * @def TEGRA186_CLK_ADSPNEON
  71. * @def TEGRA186_CLK_AHUB
  72. * @def TEGRA186_CLK_APE
  73. * @def TEGRA186_CLK_APB2APE
  74. * @def TEGRA186_CLK_AUD_MCLK
  75. * @def TEGRA186_CLK_DMIC1
  76. * @def TEGRA186_CLK_DMIC2
  77. * @def TEGRA186_CLK_DMIC3
  78. * @def TEGRA186_CLK_DMIC4
  79. * @def TEGRA186_CLK_DSPK1
  80. * @def TEGRA186_CLK_DSPK2
  81. * @def TEGRA186_CLK_HDA
  82. * @def TEGRA186_CLK_HDA2CODEC_2X
  83. * @def TEGRA186_CLK_I2S1
  84. * @def TEGRA186_CLK_I2S2
  85. * @def TEGRA186_CLK_I2S3
  86. * @def TEGRA186_CLK_I2S4
  87. * @def TEGRA186_CLK_I2S5
  88. * @def TEGRA186_CLK_I2S6
  89. * @def TEGRA186_CLK_MAUD
  90. * @def TEGRA186_CLK_PLL_A_OUT0
  91. * @def TEGRA186_CLK_SPDIF_DOUBLER
  92. * @def TEGRA186_CLK_SPDIF_IN
  93. * @def TEGRA186_CLK_SPDIF_OUT
  94. * @def TEGRA186_CLK_SYNC_DMIC1
  95. * @def TEGRA186_CLK_SYNC_DMIC2
  96. * @def TEGRA186_CLK_SYNC_DMIC3
  97. * @def TEGRA186_CLK_SYNC_DMIC4
  98. * @def TEGRA186_CLK_SYNC_DMIC5
  99. * @def TEGRA186_CLK_SYNC_DSPK1
  100. * @def TEGRA186_CLK_SYNC_DSPK2
  101. * @def TEGRA186_CLK_SYNC_I2S1
  102. * @def TEGRA186_CLK_SYNC_I2S2
  103. * @def TEGRA186_CLK_SYNC_I2S3
  104. * @def TEGRA186_CLK_SYNC_I2S4
  105. * @def TEGRA186_CLK_SYNC_I2S5
  106. * @def TEGRA186_CLK_SYNC_I2S6
  107. * @def TEGRA186_CLK_SYNC_SPDIF
  108. * @}
  109. *
  110. * @defgroup uart_clks UART clocks
  111. * @{
  112. * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
  113. * @def TEGRA186_CLK_UARTA
  114. * @def TEGRA186_CLK_UARTB
  115. * @def TEGRA186_CLK_UARTC
  116. * @def TEGRA186_CLK_UARTD
  117. * @def TEGRA186_CLK_UARTE
  118. * @def TEGRA186_CLK_UARTF
  119. * @def TEGRA186_CLK_UARTG
  120. * @def TEGRA186_CLK_UART_FST_MIPI_CAL
  121. * @}
  122. *
  123. * @defgroup i2c_clks I2C clocks
  124. * @{
  125. * @def TEGRA186_CLK_AON_I2C_SLOW
  126. * @def TEGRA186_CLK_I2C1
  127. * @def TEGRA186_CLK_I2C2
  128. * @def TEGRA186_CLK_I2C3
  129. * @def TEGRA186_CLK_I2C4
  130. * @def TEGRA186_CLK_I2C5
  131. * @def TEGRA186_CLK_I2C6
  132. * @def TEGRA186_CLK_I2C8
  133. * @def TEGRA186_CLK_I2C9
  134. * @def TEGRA186_CLK_I2C1
  135. * @def TEGRA186_CLK_I2C12
  136. * @def TEGRA186_CLK_I2C13
  137. * @def TEGRA186_CLK_I2C14
  138. * @def TEGRA186_CLK_I2C_SLOW
  139. * @def TEGRA186_CLK_VI_I2C
  140. * @}
  141. *
  142. * @defgroup spi_clks SPI clocks
  143. * @{
  144. * @def TEGRA186_CLK_SPI1
  145. * @def TEGRA186_CLK_SPI2
  146. * @def TEGRA186_CLK_SPI3
  147. * @def TEGRA186_CLK_SPI4
  148. * @}
  149. *
  150. * @defgroup storage storage related clocks
  151. * @{
  152. * @def TEGRA186_CLK_SATA
  153. * @def TEGRA186_CLK_SATA_OOB
  154. * @def TEGRA186_CLK_SATA_IOBIST
  155. * @def TEGRA186_CLK_SDMMC_LEGACY_TM
  156. * @def TEGRA186_CLK_SDMMC1
  157. * @def TEGRA186_CLK_SDMMC2
  158. * @def TEGRA186_CLK_SDMMC3
  159. * @def TEGRA186_CLK_SDMMC4
  160. * @def TEGRA186_CLK_QSPI
  161. * @def TEGRA186_CLK_QSPI_OUT
  162. * @def TEGRA186_CLK_UFSDEV_REF
  163. * @def TEGRA186_CLK_UFSHC
  164. * @}
  165. *
  166. * @defgroup pwm_clks PWM clocks
  167. * @{
  168. * @def TEGRA186_CLK_PWM1
  169. * @def TEGRA186_CLK_PWM2
  170. * @def TEGRA186_CLK_PWM3
  171. * @def TEGRA186_CLK_PWM4
  172. * @def TEGRA186_CLK_PWM5
  173. * @def TEGRA186_CLK_PWM6
  174. * @def TEGRA186_CLK_PWM7
  175. * @def TEGRA186_CLK_PWM8
  176. * @}
  177. *
  178. * @defgroup plls PLLs and related clocks
  179. * @{
  180. * @def TEGRA186_CLK_PLLREFE_OUT_GATED
  181. * @def TEGRA186_CLK_PLLREFE_OUT1
  182. * @def TEGRA186_CLK_PLLD_OUT1
  183. * @def TEGRA186_CLK_PLLP_OUT0
  184. * @def TEGRA186_CLK_PLLP_OUT5
  185. * @def TEGRA186_CLK_PLLA
  186. * @def TEGRA186_CLK_PLLE_PWRSEQ
  187. * @def TEGRA186_CLK_PLLA_OUT1
  188. * @def TEGRA186_CLK_PLLREFE_REF
  189. * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
  190. * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
  191. * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
  192. * @def TEGRA186_CLK_PLLREFE_PEX
  193. * @def TEGRA186_CLK_PLLREFE_IDDQ
  194. * @def TEGRA186_CLK_PLLC_OUT_AON
  195. * @def TEGRA186_CLK_PLLC_OUT_ISP
  196. * @def TEGRA186_CLK_PLLC_OUT_VE
  197. * @def TEGRA186_CLK_PLLC4_OUT
  198. * @def TEGRA186_CLK_PLLREFE_OUT
  199. * @def TEGRA186_CLK_PLLREFE_PLL_REF
  200. * @def TEGRA186_CLK_PLLE
  201. * @def TEGRA186_CLK_PLLC
  202. * @def TEGRA186_CLK_PLLP
  203. * @def TEGRA186_CLK_PLLD
  204. * @def TEGRA186_CLK_PLLD2
  205. * @def TEGRA186_CLK_PLLREFE_VCO
  206. * @def TEGRA186_CLK_PLLC2
  207. * @def TEGRA186_CLK_PLLC3
  208. * @def TEGRA186_CLK_PLLDP
  209. * @def TEGRA186_CLK_PLLC4_VCO
  210. * @def TEGRA186_CLK_PLLA1
  211. * @def TEGRA186_CLK_PLLNVCSI
  212. * @def TEGRA186_CLK_PLLDISPHUB
  213. * @def TEGRA186_CLK_PLLD3
  214. * @def TEGRA186_CLK_PLLBPMPCAM
  215. * @def TEGRA186_CLK_PLLAON
  216. * @def TEGRA186_CLK_PLLU
  217. * @def TEGRA186_CLK_PLLC4_VCO_DIV2
  218. * @def TEGRA186_CLK_PLL_REF
  219. * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
  220. * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
  221. * @def TEGRA186_CLK_PLL_U_48M
  222. * @def TEGRA186_CLK_PLL_U_480M
  223. * @def TEGRA186_CLK_PLLC4_OUT0
  224. * @def TEGRA186_CLK_PLLC4_OUT1
  225. * @def TEGRA186_CLK_PLLC4_OUT2
  226. * @def TEGRA186_CLK_PLLC4_OUT_MUX
  227. * @def TEGRA186_CLK_DFLLDISP_DIV
  228. * @def TEGRA186_CLK_PLLDISPHUB_DIV
  229. * @def TEGRA186_CLK_PLLP_DIV8
  230. * @}
  231. *
  232. * @defgroup nafll_clks NAFLL clock sources
  233. * @{
  234. * @def TEGRA186_CLK_NAFLL_AXI_CBB
  235. * @def TEGRA186_CLK_NAFLL_BCPU
  236. * @def TEGRA186_CLK_NAFLL_BPMP
  237. * @def TEGRA186_CLK_NAFLL_DISP
  238. * @def TEGRA186_CLK_NAFLL_GPU
  239. * @def TEGRA186_CLK_NAFLL_ISP
  240. * @def TEGRA186_CLK_NAFLL_MCPU
  241. * @def TEGRA186_CLK_NAFLL_NVDEC
  242. * @def TEGRA186_CLK_NAFLL_NVENC
  243. * @def TEGRA186_CLK_NAFLL_NVJPG
  244. * @def TEGRA186_CLK_NAFLL_SCE
  245. * @def TEGRA186_CLK_NAFLL_SE
  246. * @def TEGRA186_CLK_NAFLL_TSEC
  247. * @def TEGRA186_CLK_NAFLL_TSECB
  248. * @def TEGRA186_CLK_NAFLL_VI
  249. * @def TEGRA186_CLK_NAFLL_VIC
  250. * @}
  251. *
  252. * @defgroup mphy MPHY related clocks
  253. * @{
  254. * @def TEGRA186_CLK_MPHY_L0_RX_SYMB
  255. * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
  256. * @def TEGRA186_CLK_MPHY_L0_TX_SYMB
  257. * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
  258. * @def TEGRA186_CLK_MPHY_L0_RX_ANA
  259. * @def TEGRA186_CLK_MPHY_L1_RX_ANA
  260. * @def TEGRA186_CLK_MPHY_IOBIST
  261. * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
  262. * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
  263. * @}
  264. *
  265. * @defgroup eavb EAVB related clocks
  266. * @{
  267. * @def TEGRA186_CLK_EQOS_AXI
  268. * @def TEGRA186_CLK_EQOS_PTP_REF
  269. * @def TEGRA186_CLK_EQOS_RX
  270. * @def TEGRA186_CLK_EQOS_RX_INPUT
  271. * @def TEGRA186_CLK_EQOS_TX
  272. * @}
  273. *
  274. * @defgroup usb USB related clocks
  275. * @{
  276. * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
  277. * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
  278. * @def TEGRA186_CLK_HSIC_TRK
  279. * @def TEGRA186_CLK_USB2_TRK
  280. * @def TEGRA186_CLK_USB2_HSIC_TRK
  281. * @def TEGRA186_CLK_XUSB_CORE_SS
  282. * @def TEGRA186_CLK_XUSB_CORE_DEV
  283. * @def TEGRA186_CLK_XUSB_FALCON
  284. * @def TEGRA186_CLK_XUSB_FS
  285. * @def TEGRA186_CLK_XUSB
  286. * @def TEGRA186_CLK_XUSB_DEV
  287. * @def TEGRA186_CLK_XUSB_HOST
  288. * @def TEGRA186_CLK_XUSB_SS
  289. * @}
  290. *
  291. * @defgroup bigblock compute block related clocks
  292. * @{
  293. * @def TEGRA186_CLK_GPCCLK
  294. * @def TEGRA186_CLK_GPC2CLK
  295. * @def TEGRA186_CLK_GPU
  296. * @def TEGRA186_CLK_HOST1X
  297. * @def TEGRA186_CLK_ISP
  298. * @def TEGRA186_CLK_NVDEC
  299. * @def TEGRA186_CLK_NVENC
  300. * @def TEGRA186_CLK_NVJPG
  301. * @def TEGRA186_CLK_SE
  302. * @def TEGRA186_CLK_TSEC
  303. * @def TEGRA186_CLK_TSECB
  304. * @def TEGRA186_CLK_VIC
  305. * @}
  306. *
  307. * @defgroup can CAN bus related clocks
  308. * @{
  309. * @def TEGRA186_CLK_CAN1
  310. * @def TEGRA186_CLK_CAN1_HOST
  311. * @def TEGRA186_CLK_CAN2
  312. * @def TEGRA186_CLK_CAN2_HOST
  313. * @}
  314. *
  315. * @defgroup system basic system clocks
  316. * @{
  317. * @def TEGRA186_CLK_ACTMON
  318. * @def TEGRA186_CLK_AON_APB
  319. * @def TEGRA186_CLK_AON_CPU_NIC
  320. * @def TEGRA186_CLK_AON_NIC
  321. * @def TEGRA186_CLK_AXI_CBB
  322. * @def TEGRA186_CLK_BPMP_APB
  323. * @def TEGRA186_CLK_BPMP_CPU_NIC
  324. * @def TEGRA186_CLK_BPMP_NIC_RATE
  325. * @def TEGRA186_CLK_CLK_M
  326. * @def TEGRA186_CLK_EMC
  327. * @def TEGRA186_CLK_MSS_ENCRYPT
  328. * @def TEGRA186_CLK_SCE_APB
  329. * @def TEGRA186_CLK_SCE_CPU_NIC
  330. * @def TEGRA186_CLK_SCE_NIC
  331. * @def TEGRA186_CLK_TSC
  332. * @}
  333. *
  334. * @defgroup pcie_clks PCIe related clocks
  335. * @{
  336. * @def TEGRA186_CLK_AFI
  337. * @def TEGRA186_CLK_PCIE
  338. * @def TEGRA186_CLK_PCIE2_IOBIST
  339. * @def TEGRA186_CLK_PCIERX0
  340. * @def TEGRA186_CLK_PCIERX1
  341. * @def TEGRA186_CLK_PCIERX2
  342. * @def TEGRA186_CLK_PCIERX3
  343. * @def TEGRA186_CLK_PCIERX4
  344. * @}
  345. */
  346. /** @brief output of gate CLK_ENB_FUSE */
  347. #define TEGRA186_CLK_FUSE 0
  348. /**
  349. * @brief It's not what you think
  350. * @details output of gate CLK_ENB_GPU. This output connects to the GPU
  351. * pwrclk. @warning: This is almost certainly not the clock you think
  352. * it is. If you're looking for the clock of the graphics engine, see
  353. * TEGRA186_GPCCLK
  354. */
  355. #define TEGRA186_CLK_GPU 1
  356. /** @brief output of gate CLK_ENB_PCIE */
  357. #define TEGRA186_CLK_PCIE 3
  358. /** @brief output of the divider IPFS_CLK_DIVISOR */
  359. #define TEGRA186_CLK_AFI 4
  360. /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
  361. #define TEGRA186_CLK_PCIE2_IOBIST 5
  362. /** @brief output of gate CLK_ENB_PCIERX0*/
  363. #define TEGRA186_CLK_PCIERX0 6
  364. /** @brief output of gate CLK_ENB_PCIERX1*/
  365. #define TEGRA186_CLK_PCIERX1 7
  366. /** @brief output of gate CLK_ENB_PCIERX2*/
  367. #define TEGRA186_CLK_PCIERX2 8
  368. /** @brief output of gate CLK_ENB_PCIERX3*/
  369. #define TEGRA186_CLK_PCIERX3 9
  370. /** @brief output of gate CLK_ENB_PCIERX4*/
  371. #define TEGRA186_CLK_PCIERX4 10
  372. /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
  373. #define TEGRA186_CLK_PLLC_OUT_ISP 11
  374. /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
  375. #define TEGRA186_CLK_PLLC_OUT_VE 12
  376. /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
  377. #define TEGRA186_CLK_PLLC_OUT_AON 13
  378. /** @brief output of gate CLK_ENB_SOR_SAFE */
  379. #define TEGRA186_CLK_SOR_SAFE 39
  380. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
  381. #define TEGRA186_CLK_I2S2 42
  382. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
  383. #define TEGRA186_CLK_I2S3 43
  384. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
  385. #define TEGRA186_CLK_SPDIF_IN 44
  386. /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
  387. #define TEGRA186_CLK_SPDIF_DOUBLER 45
  388. /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
  389. #define TEGRA186_CLK_SPI3 46
  390. /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
  391. #define TEGRA186_CLK_I2C1 47
  392. /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
  393. #define TEGRA186_CLK_I2C5 48
  394. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
  395. #define TEGRA186_CLK_SPI1 49
  396. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
  397. #define TEGRA186_CLK_ISP 50
  398. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
  399. #define TEGRA186_CLK_VI 51
  400. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
  401. #define TEGRA186_CLK_SDMMC1 52
  402. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
  403. #define TEGRA186_CLK_SDMMC2 53
  404. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
  405. #define TEGRA186_CLK_SDMMC4 54
  406. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
  407. #define TEGRA186_CLK_UARTA 55
  408. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
  409. #define TEGRA186_CLK_UARTB 56
  410. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
  411. #define TEGRA186_CLK_HOST1X 57
  412. /**
  413. * @brief controls the EMC clock frequency.
  414. * @details Doing a clk_set_rate on this clock will select the
  415. * appropriate clock source, program the source rate and execute a
  416. * specific sequence to switch to the new clock source for both memory
  417. * controllers. This can be used to control the balance between memory
  418. * throughput and memory controller power.
  419. */
  420. #define TEGRA186_CLK_EMC 58
  421. /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
  422. #define TEGRA186_CLK_EXTPERIPH4 73
  423. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
  424. #define TEGRA186_CLK_SPI4 74
  425. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
  426. #define TEGRA186_CLK_I2C3 75
  427. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
  428. #define TEGRA186_CLK_SDMMC3 76
  429. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
  430. #define TEGRA186_CLK_UARTD 77
  431. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
  432. #define TEGRA186_CLK_I2S1 79
  433. /** output of gate CLK_ENB_DTV */
  434. #define TEGRA186_CLK_DTV 80
  435. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
  436. #define TEGRA186_CLK_TSEC 81
  437. /** @brief output of gate CLK_ENB_DP2 */
  438. #define TEGRA186_CLK_DP2 82
  439. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
  440. #define TEGRA186_CLK_I2S4 84
  441. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
  442. #define TEGRA186_CLK_I2S5 85
  443. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
  444. #define TEGRA186_CLK_I2C4 86
  445. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
  446. #define TEGRA186_CLK_AHUB 87
  447. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
  448. #define TEGRA186_CLK_HDA2CODEC_2X 88
  449. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
  450. #define TEGRA186_CLK_EXTPERIPH1 89
  451. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
  452. #define TEGRA186_CLK_EXTPERIPH2 90
  453. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
  454. #define TEGRA186_CLK_EXTPERIPH3 91
  455. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
  456. #define TEGRA186_CLK_I2C_SLOW 92
  457. /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
  458. #define TEGRA186_CLK_SOR1 93
  459. /** @brief output of gate CLK_ENB_CEC */
  460. #define TEGRA186_CLK_CEC 94
  461. /** @brief output of gate CLK_ENB_DPAUX1 */
  462. #define TEGRA186_CLK_DPAUX1 95
  463. /** @brief output of gate CLK_ENB_DPAUX */
  464. #define TEGRA186_CLK_DPAUX 96
  465. /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
  466. #define TEGRA186_CLK_SOR0 97
  467. /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
  468. #define TEGRA186_CLK_HDA2HDMICODEC 98
  469. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
  470. #define TEGRA186_CLK_SATA 99
  471. /** @brief output of gate CLK_ENB_SATA_OOB */
  472. #define TEGRA186_CLK_SATA_OOB 100
  473. /** @brief output of gate CLK_ENB_SATA_IOBIST */
  474. #define TEGRA186_CLK_SATA_IOBIST 101
  475. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
  476. #define TEGRA186_CLK_HDA 102
  477. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
  478. #define TEGRA186_CLK_SE 103
  479. /** @brief output of gate CLK_ENB_APB2APE */
  480. #define TEGRA186_CLK_APB2APE 104
  481. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
  482. #define TEGRA186_CLK_APE 105
  483. /** @brief output of gate CLK_ENB_IQC1 */
  484. #define TEGRA186_CLK_IQC1 106
  485. /** @brief output of gate CLK_ENB_IQC2 */
  486. #define TEGRA186_CLK_IQC2 107
  487. /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
  488. #define TEGRA186_CLK_PLLREFE_OUT 108
  489. /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
  490. #define TEGRA186_CLK_PLLREFE_PLL_REF 109
  491. /** @brief output of gate CLK_ENB_PLLC4_OUT */
  492. #define TEGRA186_CLK_PLLC4_OUT 110
  493. /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
  494. #define TEGRA186_CLK_XUSB 111
  495. /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
  496. #define TEGRA186_CLK_XUSB_DEV 112
  497. /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
  498. #define TEGRA186_CLK_XUSB_HOST 113
  499. /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
  500. #define TEGRA186_CLK_XUSB_SS 114
  501. /** @brief output of gate CLK_ENB_DSI */
  502. #define TEGRA186_CLK_DSI 115
  503. /** @brief output of gate CLK_ENB_MIPI_CAL */
  504. #define TEGRA186_CLK_MIPI_CAL 116
  505. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
  506. #define TEGRA186_CLK_DSIA_LP 117
  507. /** @brief output of gate CLK_ENB_DSIB */
  508. #define TEGRA186_CLK_DSIB 118
  509. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
  510. #define TEGRA186_CLK_DSIB_LP 119
  511. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
  512. #define TEGRA186_CLK_DMIC1 122
  513. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
  514. #define TEGRA186_CLK_DMIC2 123
  515. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
  516. #define TEGRA186_CLK_AUD_MCLK 124
  517. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
  518. #define TEGRA186_CLK_I2C6 125
  519. /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
  520. #define TEGRA186_CLK_UART_FST_MIPI_CAL 126
  521. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
  522. #define TEGRA186_CLK_VIC 127
  523. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
  524. #define TEGRA186_CLK_SDMMC_LEGACY_TM 128
  525. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
  526. #define TEGRA186_CLK_NVDEC 129
  527. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
  528. #define TEGRA186_CLK_NVJPG 130
  529. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
  530. #define TEGRA186_CLK_NVENC 131
  531. /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
  532. #define TEGRA186_CLK_QSPI 132
  533. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
  534. #define TEGRA186_CLK_VI_I2C 133
  535. /** @brief output of gate CLK_ENB_HSIC_TRK */
  536. #define TEGRA186_CLK_HSIC_TRK 134
  537. /** @brief output of gate CLK_ENB_USB2_TRK */
  538. #define TEGRA186_CLK_USB2_TRK 135
  539. /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
  540. #define TEGRA186_CLK_MAUD 136
  541. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
  542. #define TEGRA186_CLK_TSECB 137
  543. /** @brief output of gate CLK_ENB_ADSP */
  544. #define TEGRA186_CLK_ADSP 138
  545. /** @brief output of gate CLK_ENB_ADSPNEON */
  546. #define TEGRA186_CLK_ADSPNEON 139
  547. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
  548. #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
  549. /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
  550. #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
  551. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
  552. #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
  553. /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
  554. #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
  555. /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
  556. #define TEGRA186_CLK_MPHY_L0_RX_ANA 144
  557. /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
  558. #define TEGRA186_CLK_MPHY_L1_RX_ANA 145
  559. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
  560. #define TEGRA186_CLK_MPHY_IOBIST 146
  561. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
  562. #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
  563. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
  564. #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
  565. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
  566. #define TEGRA186_CLK_AXI_CBB 149
  567. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
  568. #define TEGRA186_CLK_DMIC3 150
  569. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
  570. #define TEGRA186_CLK_DMIC4 151
  571. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
  572. #define TEGRA186_CLK_DSPK1 152
  573. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
  574. #define TEGRA186_CLK_DSPK2 153
  575. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
  576. #define TEGRA186_CLK_I2S6 154
  577. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
  578. #define TEGRA186_CLK_NVDISPLAY_P0 155
  579. /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
  580. #define TEGRA186_CLK_NVDISPLAY_DISP 156
  581. /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
  582. #define TEGRA186_CLK_NVDISPLAY_DSC 157
  583. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
  584. #define TEGRA186_CLK_NVDISPLAYHUB 158
  585. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
  586. #define TEGRA186_CLK_NVDISPLAY_P1 159
  587. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
  588. #define TEGRA186_CLK_NVDISPLAY_P2 160
  589. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
  590. #define TEGRA186_CLK_TACH 166
  591. /** @brief output of gate CLK_ENB_EQOS */
  592. #define TEGRA186_CLK_EQOS_AXI 167
  593. /** @brief output of gate CLK_ENB_EQOS_RX */
  594. #define TEGRA186_CLK_EQOS_RX 168
  595. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
  596. #define TEGRA186_CLK_UFSHC 178
  597. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
  598. #define TEGRA186_CLK_UFSDEV_REF 179
  599. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
  600. #define TEGRA186_CLK_NVCSI 180
  601. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
  602. #define TEGRA186_CLK_NVCSILP 181
  603. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
  604. #define TEGRA186_CLK_I2C7 182
  605. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
  606. #define TEGRA186_CLK_I2C9 183
  607. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
  608. #define TEGRA186_CLK_I2C12 184
  609. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
  610. #define TEGRA186_CLK_I2C13 185
  611. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
  612. #define TEGRA186_CLK_I2C14 186
  613. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
  614. #define TEGRA186_CLK_PWM1 187
  615. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
  616. #define TEGRA186_CLK_PWM2 188
  617. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
  618. #define TEGRA186_CLK_PWM3 189
  619. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
  620. #define TEGRA186_CLK_PWM5 190
  621. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
  622. #define TEGRA186_CLK_PWM6 191
  623. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
  624. #define TEGRA186_CLK_PWM7 192
  625. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
  626. #define TEGRA186_CLK_PWM8 193
  627. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
  628. #define TEGRA186_CLK_UARTE 194
  629. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
  630. #define TEGRA186_CLK_UARTF 195
  631. /** @deprecated */
  632. #define TEGRA186_CLK_DBGAPB 196
  633. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
  634. #define TEGRA186_CLK_BPMP_CPU_NIC 197
  635. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
  636. #define TEGRA186_CLK_BPMP_APB 199
  637. /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
  638. #define TEGRA186_CLK_ACTMON 201
  639. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
  640. #define TEGRA186_CLK_AON_CPU_NIC 208
  641. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
  642. #define TEGRA186_CLK_CAN1 210
  643. /** @brief output of gate CLK_ENB_CAN1_HOST */
  644. #define TEGRA186_CLK_CAN1_HOST 211
  645. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
  646. #define TEGRA186_CLK_CAN2 212
  647. /** @brief output of gate CLK_ENB_CAN2_HOST */
  648. #define TEGRA186_CLK_CAN2_HOST 213
  649. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
  650. #define TEGRA186_CLK_AON_APB 214
  651. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
  652. #define TEGRA186_CLK_UARTC 215
  653. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
  654. #define TEGRA186_CLK_UARTG 216
  655. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
  656. #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
  657. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
  658. #define TEGRA186_CLK_I2C2 218
  659. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
  660. #define TEGRA186_CLK_I2C8 219
  661. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
  662. #define TEGRA186_CLK_I2C10 220
  663. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
  664. #define TEGRA186_CLK_AON_I2C_SLOW 221
  665. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
  666. #define TEGRA186_CLK_SPI2 222
  667. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
  668. #define TEGRA186_CLK_DMIC5 223
  669. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
  670. #define TEGRA186_CLK_AON_TOUCH 224
  671. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
  672. #define TEGRA186_CLK_PWM4 225
  673. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
  674. #define TEGRA186_CLK_TSC 226
  675. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
  676. #define TEGRA186_CLK_MSS_ENCRYPT 227
  677. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
  678. #define TEGRA186_CLK_SCE_CPU_NIC 228
  679. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
  680. #define TEGRA186_CLK_SCE_APB 230
  681. /** @brief output of gate CLK_ENB_DSIC */
  682. #define TEGRA186_CLK_DSIC 231
  683. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
  684. #define TEGRA186_CLK_DSIC_LP 232
  685. /** @brief output of gate CLK_ENB_DSID */
  686. #define TEGRA186_CLK_DSID 233
  687. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
  688. #define TEGRA186_CLK_DSID_LP 234
  689. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
  690. #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
  691. /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
  692. #define TEGRA186_CLK_SPDIF_OUT 238
  693. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
  694. #define TEGRA186_CLK_EQOS_PTP_REF 239
  695. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
  696. #define TEGRA186_CLK_EQOS_TX 240
  697. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
  698. #define TEGRA186_CLK_USB2_HSIC_TRK 241
  699. /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
  700. #define TEGRA186_CLK_XUSB_CORE_SS 242
  701. /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
  702. #define TEGRA186_CLK_XUSB_CORE_DEV 243
  703. /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
  704. #define TEGRA186_CLK_XUSB_FALCON 244
  705. /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
  706. #define TEGRA186_CLK_XUSB_FS 245
  707. /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
  708. #define TEGRA186_CLK_PLL_A_OUT0 246
  709. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
  710. #define TEGRA186_CLK_SYNC_I2S1 247
  711. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
  712. #define TEGRA186_CLK_SYNC_I2S2 248
  713. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
  714. #define TEGRA186_CLK_SYNC_I2S3 249
  715. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
  716. #define TEGRA186_CLK_SYNC_I2S4 250
  717. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
  718. #define TEGRA186_CLK_SYNC_I2S5 251
  719. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
  720. #define TEGRA186_CLK_SYNC_I2S6 252
  721. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
  722. #define TEGRA186_CLK_SYNC_DSPK1 253
  723. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
  724. #define TEGRA186_CLK_SYNC_DSPK2 254
  725. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
  726. #define TEGRA186_CLK_SYNC_DMIC1 255
  727. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
  728. #define TEGRA186_CLK_SYNC_DMIC2 256
  729. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
  730. #define TEGRA186_CLK_SYNC_DMIC3 257
  731. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
  732. #define TEGRA186_CLK_SYNC_DMIC4 259
  733. /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
  734. #define TEGRA186_CLK_SYNC_SPDIF 260
  735. /** @brief output of gate CLK_ENB_PLLREFE_OUT */
  736. #define TEGRA186_CLK_PLLREFE_OUT_GATED 261
  737. /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
  738. * * VCO/pdiv defined by this clock object
  739. * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
  740. */
  741. #define TEGRA186_CLK_PLLREFE_OUT1 262
  742. #define TEGRA186_CLK_PLLD_OUT1 267
  743. /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
  744. #define TEGRA186_CLK_PLLP_OUT0 269
  745. /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
  746. #define TEGRA186_CLK_PLLP_OUT5 270
  747. /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
  748. #define TEGRA186_CLK_PLLA 271
  749. /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
  750. #define TEGRA186_CLK_ACLK 273
  751. /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
  752. #define TEGRA186_CLK_PLL_U_48M 274
  753. /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
  754. #define TEGRA186_CLK_PLL_U_480M 275
  755. /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
  756. #define TEGRA186_CLK_PLLC4_OUT0 276
  757. /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
  758. #define TEGRA186_CLK_PLLC4_OUT1 277
  759. /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
  760. #define TEGRA186_CLK_PLLC4_OUT2 278
  761. /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
  762. #define TEGRA186_CLK_PLLC4_OUT_MUX 279
  763. /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
  764. #define TEGRA186_CLK_DFLLDISP_DIV 284
  765. /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
  766. #define TEGRA186_CLK_PLLDISPHUB_DIV 285
  767. /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
  768. #define TEGRA186_CLK_PLLP_DIV8 286
  769. /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
  770. #define TEGRA186_CLK_BPMP_NIC 287
  771. /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
  772. #define TEGRA186_CLK_PLL_A_OUT1 288
  773. /** @deprecated */
  774. #define TEGRA186_CLK_GPC2CLK 289
  775. /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
  776. #define TEGRA186_CLK_KFUSE 293
  777. /**
  778. * @brief controls the PLLE hardware sequencer.
  779. * @details This clock only has enable and disable methods. When the
  780. * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
  781. * hw based on the control signals from the PCIe, SATA and XUSB
  782. * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
  783. * is controlled by sw using clk_enable/clk_disable on
  784. * TEGRA186_CLK_PLLE.
  785. */
  786. #define TEGRA186_CLK_PLLE_PWRSEQ 294
  787. /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
  788. #define TEGRA186_CLK_PLLREFE_REF 295
  789. /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
  790. #define TEGRA186_CLK_SOR0_OUT 296
  791. /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
  792. #define TEGRA186_CLK_SOR1_OUT 297
  793. /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
  794. #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
  795. /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
  796. #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
  797. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
  798. #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
  799. /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
  800. #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
  801. /** @brief controls the UPHY_PLL0 hardware sqeuencer */
  802. #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
  803. /** @brief controls the UPHY_PLL1 hardware sqeuencer */
  804. #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
  805. /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
  806. #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
  807. /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
  808. #define TEGRA186_CLK_PLLREFE_PEX 307
  809. /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
  810. #define TEGRA186_CLK_PLLREFE_IDDQ 308
  811. /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
  812. #define TEGRA186_CLK_QSPI_OUT 309
  813. /**
  814. * @brief GPC2CLK-div-2
  815. * @details fixed /2 divider. Output frequency is
  816. * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
  817. * frequency at which the GPU graphics engine runs. */
  818. #define TEGRA186_CLK_GPCCLK 310
  819. /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
  820. #define TEGRA186_CLK_AON_NIC 450
  821. /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
  822. #define TEGRA186_CLK_SCE_NIC 451
  823. /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
  824. #define TEGRA186_CLK_PLLE 512
  825. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
  826. #define TEGRA186_CLK_PLLC 513
  827. /** Fixed 408MHz PLL for use by peripheral clocks */
  828. #define TEGRA186_CLK_PLLP 516
  829. /** @deprecated */
  830. #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
  831. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
  832. #define TEGRA186_CLK_PLLD 518
  833. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
  834. #define TEGRA186_CLK_PLLD2 519
  835. /**
  836. * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
  837. * @details Note that this clock only controls the VCO output, before
  838. * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
  839. * information.
  840. */
  841. #define TEGRA186_CLK_PLLREFE_VCO 520
  842. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
  843. #define TEGRA186_CLK_PLLC2 521
  844. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
  845. #define TEGRA186_CLK_PLLC3 522
  846. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
  847. #define TEGRA186_CLK_PLLDP 523
  848. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
  849. #define TEGRA186_CLK_PLLC4_VCO 524
  850. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
  851. #define TEGRA186_CLK_PLLA1 525
  852. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
  853. #define TEGRA186_CLK_PLLNVCSI 526
  854. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
  855. #define TEGRA186_CLK_PLLDISPHUB 527
  856. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
  857. #define TEGRA186_CLK_PLLD3 528
  858. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
  859. #define TEGRA186_CLK_PLLBPMPCAM 531
  860. /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
  861. #define TEGRA186_CLK_PLLAON 532
  862. /** Fixed frequency 960MHz PLL for USB and EAVB */
  863. #define TEGRA186_CLK_PLLU 533
  864. /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
  865. #define TEGRA186_CLK_PLLC4_VCO_DIV2 535
  866. /** @brief NAFLL clock source for AXI_CBB */
  867. #define TEGRA186_CLK_NAFLL_AXI_CBB 564
  868. /** @brief NAFLL clock source for BPMP */
  869. #define TEGRA186_CLK_NAFLL_BPMP 565
  870. /** @brief NAFLL clock source for ISP */
  871. #define TEGRA186_CLK_NAFLL_ISP 566
  872. /** @brief NAFLL clock source for NVDEC */
  873. #define TEGRA186_CLK_NAFLL_NVDEC 567
  874. /** @brief NAFLL clock source for NVENC */
  875. #define TEGRA186_CLK_NAFLL_NVENC 568
  876. /** @brief NAFLL clock source for NVJPG */
  877. #define TEGRA186_CLK_NAFLL_NVJPG 569
  878. /** @brief NAFLL clock source for SCE */
  879. #define TEGRA186_CLK_NAFLL_SCE 570
  880. /** @brief NAFLL clock source for SE */
  881. #define TEGRA186_CLK_NAFLL_SE 571
  882. /** @brief NAFLL clock source for TSEC */
  883. #define TEGRA186_CLK_NAFLL_TSEC 572
  884. /** @brief NAFLL clock source for TSECB */
  885. #define TEGRA186_CLK_NAFLL_TSECB 573
  886. /** @brief NAFLL clock source for VI */
  887. #define TEGRA186_CLK_NAFLL_VI 574
  888. /** @brief NAFLL clock source for VIC */
  889. #define TEGRA186_CLK_NAFLL_VIC 575
  890. /** @brief NAFLL clock source for DISP */
  891. #define TEGRA186_CLK_NAFLL_DISP 576
  892. /** @brief NAFLL clock source for GPU */
  893. #define TEGRA186_CLK_NAFLL_GPU 577
  894. /** @brief NAFLL clock source for M-CPU cluster */
  895. #define TEGRA186_CLK_NAFLL_MCPU 578
  896. /** @brief NAFLL clock source for B-CPU cluster */
  897. #define TEGRA186_CLK_NAFLL_BCPU 579
  898. /** @brief input from Tegra's CLK_32K_IN pad */
  899. #define TEGRA186_CLK_CLK_32K 608
  900. /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
  901. #define TEGRA186_CLK_CLK_M 609
  902. /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
  903. #define TEGRA186_CLK_PLL_REF 610
  904. /** @brief input from Tegra's XTAL_IN */
  905. #define TEGRA186_CLK_OSC 612
  906. /** @brief clock recovered from EAVB input */
  907. #define TEGRA186_CLK_EQOS_RX_INPUT 613
  908. /** @brief clock recovered from DTV input */
  909. #define TEGRA186_CLK_DTV_INPUT 614
  910. /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
  911. #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
  912. /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
  913. #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
  914. /** @brief clock recovered from I2S1 input */
  915. #define TEGRA186_CLK_I2S1_SYNC_INPUT 617
  916. /** @brief clock recovered from I2S2 input */
  917. #define TEGRA186_CLK_I2S2_SYNC_INPUT 618
  918. /** @brief clock recovered from I2S3 input */
  919. #define TEGRA186_CLK_I2S3_SYNC_INPUT 619
  920. /** @brief clock recovered from I2S4 input */
  921. #define TEGRA186_CLK_I2S4_SYNC_INPUT 620
  922. /** @brief clock recovered from I2S5 input */
  923. #define TEGRA186_CLK_I2S5_SYNC_INPUT 621
  924. /** @brief clock recovered from I2S6 input */
  925. #define TEGRA186_CLK_I2S6_SYNC_INPUT 622
  926. /** @brief clock recovered from SPDIFIN input */
  927. #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
  928. /**
  929. * @brief subject to change
  930. * @details maximum clock identifier value plus one.
  931. */
  932. #define TEGRA186_CLK_CLK_MAX 624
  933. /** @} */
  934. #endif