tegra114-car.h 8.0 KB

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  1. /*
  2. * This header provides constants for binding nvidia,tegra114-car.
  3. *
  4. * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
  5. * registers. These IDs often match those in the CAR's RST_DEVICES registers,
  6. * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
  7. * this case, those clocks are assigned IDs above 160 in order to highlight
  8. * this issue. Implementations that interpret these clock IDs as bit values
  9. * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
  10. * explicitly handle these special cases.
  11. *
  12. * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
  13. * above.
  14. */
  15. #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
  16. #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
  17. /* 0 */
  18. /* 1 */
  19. /* 2 */
  20. /* 3 */
  21. #define TEGRA114_CLK_RTC 4
  22. #define TEGRA114_CLK_TIMER 5
  23. #define TEGRA114_CLK_UARTA 6
  24. /* 7 (register bit affects uartb and vfir) */
  25. /* 8 */
  26. #define TEGRA114_CLK_SDMMC2 9
  27. /* 10 (register bit affects spdif_in and spdif_out) */
  28. #define TEGRA114_CLK_I2S1 11
  29. #define TEGRA114_CLK_I2C1 12
  30. #define TEGRA114_CLK_NDFLASH 13
  31. #define TEGRA114_CLK_SDMMC1 14
  32. #define TEGRA114_CLK_SDMMC4 15
  33. /* 16 */
  34. #define TEGRA114_CLK_PWM 17
  35. #define TEGRA114_CLK_I2S2 18
  36. #define TEGRA114_CLK_EPP 19
  37. /* 20 (register bit affects vi and vi_sensor) */
  38. #define TEGRA114_CLK_GR2D 21
  39. #define TEGRA114_CLK_USBD 22
  40. #define TEGRA114_CLK_ISP 23
  41. #define TEGRA114_CLK_GR3D 24
  42. /* 25 */
  43. #define TEGRA114_CLK_DISP2 26
  44. #define TEGRA114_CLK_DISP1 27
  45. #define TEGRA114_CLK_HOST1X 28
  46. #define TEGRA114_CLK_VCP 29
  47. #define TEGRA114_CLK_I2S0 30
  48. /* 31 */
  49. #define TEGRA114_CLK_MC 32
  50. /* 33 */
  51. #define TEGRA114_CLK_APBDMA 34
  52. /* 35 */
  53. #define TEGRA114_CLK_KBC 36
  54. /* 37 */
  55. /* 38 */
  56. /* 39 (register bit affects fuse and fuse_burn) */
  57. #define TEGRA114_CLK_KFUSE 40
  58. #define TEGRA114_CLK_SBC1 41
  59. #define TEGRA114_CLK_NOR 42
  60. /* 43 */
  61. #define TEGRA114_CLK_SBC2 44
  62. /* 45 */
  63. #define TEGRA114_CLK_SBC3 46
  64. #define TEGRA114_CLK_I2C5 47
  65. #define TEGRA114_CLK_DSIA 48
  66. /* 49 */
  67. #define TEGRA114_CLK_MIPI 50
  68. #define TEGRA114_CLK_HDMI 51
  69. #define TEGRA114_CLK_CSI 52
  70. /* 53 */
  71. #define TEGRA114_CLK_I2C2 54
  72. #define TEGRA114_CLK_UARTC 55
  73. #define TEGRA114_CLK_MIPI_CAL 56
  74. #define TEGRA114_CLK_EMC 57
  75. #define TEGRA114_CLK_USB2 58
  76. #define TEGRA114_CLK_USB3 59
  77. /* 60 */
  78. #define TEGRA114_CLK_VDE 61
  79. #define TEGRA114_CLK_BSEA 62
  80. #define TEGRA114_CLK_BSEV 63
  81. /* 64 */
  82. #define TEGRA114_CLK_UARTD 65
  83. /* 66 */
  84. #define TEGRA114_CLK_I2C3 67
  85. #define TEGRA114_CLK_SBC4 68
  86. #define TEGRA114_CLK_SDMMC3 69
  87. /* 70 */
  88. #define TEGRA114_CLK_OWR 71
  89. /* 72 */
  90. #define TEGRA114_CLK_CSITE 73
  91. /* 74 */
  92. /* 75 */
  93. #define TEGRA114_CLK_LA 76
  94. #define TEGRA114_CLK_TRACE 77
  95. #define TEGRA114_CLK_SOC_THERM 78
  96. #define TEGRA114_CLK_DTV 79
  97. #define TEGRA114_CLK_NDSPEED 80
  98. #define TEGRA114_CLK_I2CSLOW 81
  99. #define TEGRA114_CLK_DSIB 82
  100. #define TEGRA114_CLK_TSEC 83
  101. /* 84 */
  102. /* 85 */
  103. /* 86 */
  104. /* 87 */
  105. /* 88 */
  106. #define TEGRA114_CLK_XUSB_HOST 89
  107. /* 90 */
  108. #define TEGRA114_CLK_MSENC 91
  109. #define TEGRA114_CLK_CSUS 92
  110. /* 93 */
  111. /* 94 */
  112. /* 95 (bit affects xusb_dev and xusb_dev_src) */
  113. /* 96 */
  114. /* 97 */
  115. /* 98 */
  116. #define TEGRA114_CLK_MSELECT 99
  117. #define TEGRA114_CLK_TSENSOR 100
  118. #define TEGRA114_CLK_I2S3 101
  119. #define TEGRA114_CLK_I2S4 102
  120. #define TEGRA114_CLK_I2C4 103
  121. #define TEGRA114_CLK_SBC5 104
  122. #define TEGRA114_CLK_SBC6 105
  123. #define TEGRA114_CLK_D_AUDIO 106
  124. #define TEGRA114_CLK_APBIF 107
  125. #define TEGRA114_CLK_DAM0 108
  126. #define TEGRA114_CLK_DAM1 109
  127. #define TEGRA114_CLK_DAM2 110
  128. #define TEGRA114_CLK_HDA2CODEC_2X 111
  129. /* 112 */
  130. #define TEGRA114_CLK_AUDIO0_2X 113
  131. #define TEGRA114_CLK_AUDIO1_2X 114
  132. #define TEGRA114_CLK_AUDIO2_2X 115
  133. #define TEGRA114_CLK_AUDIO3_2X 116
  134. #define TEGRA114_CLK_AUDIO4_2X 117
  135. #define TEGRA114_CLK_SPDIF_2X 118
  136. #define TEGRA114_CLK_ACTMON 119
  137. #define TEGRA114_CLK_EXTERN1 120
  138. #define TEGRA114_CLK_EXTERN2 121
  139. #define TEGRA114_CLK_EXTERN3 122
  140. /* 123 */
  141. /* 124 */
  142. #define TEGRA114_CLK_HDA 125
  143. /* 126 */
  144. #define TEGRA114_CLK_SE 127
  145. #define TEGRA114_CLK_HDA2HDMI 128
  146. /* 129 */
  147. /* 130 */
  148. /* 131 */
  149. /* 132 */
  150. /* 133 */
  151. /* 134 */
  152. /* 135 */
  153. /* 136 */
  154. /* 137 */
  155. /* 138 */
  156. /* 139 */
  157. /* 140 */
  158. /* 141 */
  159. /* 142 */
  160. /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
  161. /* xusb_host_src and xusb_ss_src) */
  162. #define TEGRA114_CLK_CILAB 144
  163. #define TEGRA114_CLK_CILCD 145
  164. #define TEGRA114_CLK_CILE 146
  165. #define TEGRA114_CLK_DSIALP 147
  166. #define TEGRA114_CLK_DSIBLP 148
  167. /* 149 */
  168. #define TEGRA114_CLK_DDS 150
  169. /* 151 */
  170. #define TEGRA114_CLK_DP2 152
  171. #define TEGRA114_CLK_AMX 153
  172. #define TEGRA114_CLK_ADX 154
  173. /* 155 (bit affects dfll_ref and dfll_soc) */
  174. #define TEGRA114_CLK_XUSB_SS 156
  175. /* 157 */
  176. /* 158 */
  177. /* 159 */
  178. /* 160 */
  179. /* 161 */
  180. /* 162 */
  181. /* 163 */
  182. /* 164 */
  183. /* 165 */
  184. /* 166 */
  185. /* 167 */
  186. /* 168 */
  187. /* 169 */
  188. /* 170 */
  189. /* 171 */
  190. /* 172 */
  191. /* 173 */
  192. /* 174 */
  193. /* 175 */
  194. /* 176 */
  195. /* 177 */
  196. /* 178 */
  197. /* 179 */
  198. /* 180 */
  199. /* 181 */
  200. /* 182 */
  201. /* 183 */
  202. /* 184 */
  203. /* 185 */
  204. /* 186 */
  205. /* 187 */
  206. /* 188 */
  207. /* 189 */
  208. /* 190 */
  209. /* 191 */
  210. #define TEGRA114_CLK_UARTB 192
  211. #define TEGRA114_CLK_VFIR 193
  212. #define TEGRA114_CLK_SPDIF_IN 194
  213. #define TEGRA114_CLK_SPDIF_OUT 195
  214. #define TEGRA114_CLK_VI 196
  215. #define TEGRA114_CLK_VI_SENSOR 197
  216. #define TEGRA114_CLK_FUSE 198
  217. #define TEGRA114_CLK_FUSE_BURN 199
  218. #define TEGRA114_CLK_CLK_32K 200
  219. #define TEGRA114_CLK_CLK_M 201
  220. #define TEGRA114_CLK_CLK_M_DIV2 202
  221. #define TEGRA114_CLK_CLK_M_DIV4 203
  222. #define TEGRA114_CLK_PLL_REF 204
  223. #define TEGRA114_CLK_PLL_C 205
  224. #define TEGRA114_CLK_PLL_C_OUT1 206
  225. #define TEGRA114_CLK_PLL_C2 207
  226. #define TEGRA114_CLK_PLL_C3 208
  227. #define TEGRA114_CLK_PLL_M 209
  228. #define TEGRA114_CLK_PLL_M_OUT1 210
  229. #define TEGRA114_CLK_PLL_P 211
  230. #define TEGRA114_CLK_PLL_P_OUT1 212
  231. #define TEGRA114_CLK_PLL_P_OUT2 213
  232. #define TEGRA114_CLK_PLL_P_OUT3 214
  233. #define TEGRA114_CLK_PLL_P_OUT4 215
  234. #define TEGRA114_CLK_PLL_A 216
  235. #define TEGRA114_CLK_PLL_A_OUT0 217
  236. #define TEGRA114_CLK_PLL_D 218
  237. #define TEGRA114_CLK_PLL_D_OUT0 219
  238. #define TEGRA114_CLK_PLL_D2 220
  239. #define TEGRA114_CLK_PLL_D2_OUT0 221
  240. #define TEGRA114_CLK_PLL_U 222
  241. #define TEGRA114_CLK_PLL_U_480M 223
  242. #define TEGRA114_CLK_PLL_U_60M 224
  243. #define TEGRA114_CLK_PLL_U_48M 225
  244. #define TEGRA114_CLK_PLL_U_12M 226
  245. #define TEGRA114_CLK_PLL_X 227
  246. #define TEGRA114_CLK_PLL_X_OUT0 228
  247. #define TEGRA114_CLK_PLL_RE_VCO 229
  248. #define TEGRA114_CLK_PLL_RE_OUT 230
  249. #define TEGRA114_CLK_PLL_E_OUT0 231
  250. #define TEGRA114_CLK_SPDIF_IN_SYNC 232
  251. #define TEGRA114_CLK_I2S0_SYNC 233
  252. #define TEGRA114_CLK_I2S1_SYNC 234
  253. #define TEGRA114_CLK_I2S2_SYNC 235
  254. #define TEGRA114_CLK_I2S3_SYNC 236
  255. #define TEGRA114_CLK_I2S4_SYNC 237
  256. #define TEGRA114_CLK_VIMCLK_SYNC 238
  257. #define TEGRA114_CLK_AUDIO0 239
  258. #define TEGRA114_CLK_AUDIO1 240
  259. #define TEGRA114_CLK_AUDIO2 241
  260. #define TEGRA114_CLK_AUDIO3 242
  261. #define TEGRA114_CLK_AUDIO4 243
  262. #define TEGRA114_CLK_SPDIF 244
  263. #define TEGRA114_CLK_CLK_OUT_1 245
  264. #define TEGRA114_CLK_CLK_OUT_2 246
  265. #define TEGRA114_CLK_CLK_OUT_3 247
  266. #define TEGRA114_CLK_BLINK 248
  267. /* 249 */
  268. /* 250 */
  269. /* 251 */
  270. #define TEGRA114_CLK_XUSB_HOST_SRC 252
  271. #define TEGRA114_CLK_XUSB_FALCON_SRC 253
  272. #define TEGRA114_CLK_XUSB_FS_SRC 254
  273. #define TEGRA114_CLK_XUSB_SS_SRC 255
  274. #define TEGRA114_CLK_XUSB_DEV_SRC 256
  275. #define TEGRA114_CLK_XUSB_DEV 257
  276. #define TEGRA114_CLK_XUSB_HS_SRC 258
  277. #define TEGRA114_CLK_SCLK 259
  278. #define TEGRA114_CLK_HCLK 260
  279. #define TEGRA114_CLK_PCLK 261
  280. #define TEGRA114_CLK_CCLK_G 262
  281. #define TEGRA114_CLK_CCLK_LP 263
  282. #define TEGRA114_CLK_DFLL_REF 264
  283. #define TEGRA114_CLK_DFLL_SOC 265
  284. /* 266 */
  285. /* 267 */
  286. /* 268 */
  287. /* 269 */
  288. /* 270 */
  289. /* 271 */
  290. /* 272 */
  291. /* 273 */
  292. /* 274 */
  293. /* 275 */
  294. /* 276 */
  295. /* 277 */
  296. /* 278 */
  297. /* 279 */
  298. /* 280 */
  299. /* 281 */
  300. /* 282 */
  301. /* 283 */
  302. /* 284 */
  303. /* 285 */
  304. /* 286 */
  305. /* 287 */
  306. /* 288 */
  307. /* 289 */
  308. /* 290 */
  309. /* 291 */
  310. /* 292 */
  311. /* 293 */
  312. /* 294 */
  313. /* 295 */
  314. /* 296 */
  315. /* 297 */
  316. /* 298 */
  317. /* 299 */
  318. #define TEGRA114_CLK_AUDIO0_MUX 300
  319. #define TEGRA114_CLK_AUDIO1_MUX 301
  320. #define TEGRA114_CLK_AUDIO2_MUX 302
  321. #define TEGRA114_CLK_AUDIO3_MUX 303
  322. #define TEGRA114_CLK_AUDIO4_MUX 304
  323. #define TEGRA114_CLK_SPDIF_MUX 305
  324. #define TEGRA114_CLK_CLK_OUT_1_MUX 306
  325. #define TEGRA114_CLK_CLK_OUT_2_MUX 307
  326. #define TEGRA114_CLK_CLK_OUT_3_MUX 308
  327. #define TEGRA114_CLK_DSIA_MUX 309
  328. #define TEGRA114_CLK_DSIB_MUX 310
  329. #define TEGRA114_CLK_XUSB_SS_DIV2 311
  330. #define TEGRA114_CLK_CLK_MAX 312
  331. #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */