rk3368-cru.h 9.1 KB

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  1. /*
  2. * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
  15. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
  16. /* core clocks */
  17. #define PLL_APLLB 1
  18. #define PLL_APLLL 2
  19. #define PLL_DPLL 3
  20. #define PLL_CPLL 4
  21. #define PLL_GPLL 5
  22. #define PLL_NPLL 6
  23. #define ARMCLKB 7
  24. #define ARMCLKL 8
  25. /* sclk gates (special clocks) */
  26. #define SCLK_GPU_CORE 64
  27. #define SCLK_SPI0 65
  28. #define SCLK_SPI1 66
  29. #define SCLK_SPI2 67
  30. #define SCLK_SDMMC 68
  31. #define SCLK_SDIO0 69
  32. #define SCLK_EMMC 71
  33. #define SCLK_TSADC 72
  34. #define SCLK_SARADC 73
  35. #define SCLK_NANDC0 75
  36. #define SCLK_UART0 77
  37. #define SCLK_UART1 78
  38. #define SCLK_UART2 79
  39. #define SCLK_UART3 80
  40. #define SCLK_UART4 81
  41. #define SCLK_I2S_8CH 82
  42. #define SCLK_SPDIF_8CH 83
  43. #define SCLK_I2S_2CH 84
  44. #define SCLK_TIMER0 85
  45. #define SCLK_TIMER1 86
  46. #define SCLK_TIMER2 87
  47. #define SCLK_TIMER3 88
  48. #define SCLK_TIMER4 89
  49. #define SCLK_TIMER5 90
  50. #define SCLK_TIMER6 91
  51. #define SCLK_OTGPHY0 93
  52. #define SCLK_OTG_ADP 96
  53. #define SCLK_HSICPHY480M 97
  54. #define SCLK_HSICPHY12M 98
  55. #define SCLK_MACREF 99
  56. #define SCLK_VOP0_PWM 100
  57. #define SCLK_MAC_RX 102
  58. #define SCLK_MAC_TX 103
  59. #define SCLK_EDP_24M 104
  60. #define SCLK_EDP 105
  61. #define SCLK_RGA 106
  62. #define SCLK_ISP 107
  63. #define SCLK_HDCP 108
  64. #define SCLK_HDMI_HDCP 109
  65. #define SCLK_HDMI_CEC 110
  66. #define SCLK_HEVC_CABAC 111
  67. #define SCLK_HEVC_CORE 112
  68. #define SCLK_I2S_8CH_OUT 113
  69. #define SCLK_SDMMC_DRV 114
  70. #define SCLK_SDIO0_DRV 115
  71. #define SCLK_EMMC_DRV 117
  72. #define SCLK_SDMMC_SAMPLE 118
  73. #define SCLK_SDIO0_SAMPLE 119
  74. #define SCLK_EMMC_SAMPLE 121
  75. #define SCLK_USBPHY480M 122
  76. #define SCLK_PVTM_CORE 123
  77. #define SCLK_PVTM_GPU 124
  78. #define SCLK_PVTM_PMU 125
  79. #define SCLK_SFC 126
  80. #define SCLK_MAC 127
  81. #define SCLK_MACREF_OUT 128
  82. #define DCLK_VOP 190
  83. #define MCLK_CRYPTO 191
  84. /* aclk gates */
  85. #define ACLK_GPU_MEM 192
  86. #define ACLK_GPU_CFG 193
  87. #define ACLK_DMAC_BUS 194
  88. #define ACLK_DMAC_PERI 195
  89. #define ACLK_PERI_MMU 196
  90. #define ACLK_GMAC 197
  91. #define ACLK_VOP 198
  92. #define ACLK_VOP_IEP 199
  93. #define ACLK_RGA 200
  94. #define ACLK_HDCP 201
  95. #define ACLK_IEP 202
  96. #define ACLK_VIO0_NOC 203
  97. #define ACLK_VIP 204
  98. #define ACLK_ISP 205
  99. #define ACLK_VIO1_NOC 206
  100. #define ACLK_VIDEO 208
  101. #define ACLK_BUS 209
  102. #define ACLK_PERI 210
  103. /* pclk gates */
  104. #define PCLK_GPIO0 320
  105. #define PCLK_GPIO1 321
  106. #define PCLK_GPIO2 322
  107. #define PCLK_GPIO3 323
  108. #define PCLK_PMUGRF 324
  109. #define PCLK_MAILBOX 325
  110. #define PCLK_GRF 329
  111. #define PCLK_SGRF 330
  112. #define PCLK_PMU 331
  113. #define PCLK_I2C0 332
  114. #define PCLK_I2C1 333
  115. #define PCLK_I2C2 334
  116. #define PCLK_I2C3 335
  117. #define PCLK_I2C4 336
  118. #define PCLK_I2C5 337
  119. #define PCLK_SPI0 338
  120. #define PCLK_SPI1 339
  121. #define PCLK_SPI2 340
  122. #define PCLK_UART0 341
  123. #define PCLK_UART1 342
  124. #define PCLK_UART2 343
  125. #define PCLK_UART3 344
  126. #define PCLK_UART4 345
  127. #define PCLK_TSADC 346
  128. #define PCLK_SARADC 347
  129. #define PCLK_SIM 348
  130. #define PCLK_GMAC 349
  131. #define PCLK_PWM0 350
  132. #define PCLK_PWM1 351
  133. #define PCLK_TIMER0 353
  134. #define PCLK_TIMER1 354
  135. #define PCLK_EDP_CTRL 355
  136. #define PCLK_MIPI_DSI0 356
  137. #define PCLK_MIPI_CSI 358
  138. #define PCLK_HDCP 359
  139. #define PCLK_HDMI_CTRL 360
  140. #define PCLK_VIO_H2P 361
  141. #define PCLK_BUS 362
  142. #define PCLK_PERI 363
  143. #define PCLK_DDRUPCTL 364
  144. #define PCLK_DDRPHY 365
  145. #define PCLK_ISP 366
  146. #define PCLK_VIP 367
  147. #define PCLK_WDT 368
  148. /* hclk gates */
  149. #define HCLK_SFC 448
  150. #define HCLK_OTG0 449
  151. #define HCLK_HOST0 450
  152. #define HCLK_HOST1 451
  153. #define HCLK_HSIC 452
  154. #define HCLK_NANDC0 453
  155. #define HCLK_TSP 455
  156. #define HCLK_SDMMC 456
  157. #define HCLK_SDIO0 457
  158. #define HCLK_EMMC 459
  159. #define HCLK_HSADC 460
  160. #define HCLK_CRYPTO 461
  161. #define HCLK_I2S_2CH 462
  162. #define HCLK_I2S_8CH 463
  163. #define HCLK_SPDIF 464
  164. #define HCLK_VOP 465
  165. #define HCLK_ROM 467
  166. #define HCLK_IEP 468
  167. #define HCLK_ISP 469
  168. #define HCLK_RGA 470
  169. #define HCLK_VIO_AHB_ARBI 471
  170. #define HCLK_VIO_NOC 472
  171. #define HCLK_VIP 473
  172. #define HCLK_VIO_H2P 474
  173. #define HCLK_VIO_HDCPMMU 475
  174. #define HCLK_VIDEO 476
  175. #define HCLK_BUS 477
  176. #define HCLK_PERI 478
  177. #define CLK_NR_CLKS (HCLK_PERI + 1)
  178. /* soft-reset indices */
  179. #define SRST_CORE_B0 0
  180. #define SRST_CORE_B1 1
  181. #define SRST_CORE_B2 2
  182. #define SRST_CORE_B3 3
  183. #define SRST_CORE_B0_PO 4
  184. #define SRST_CORE_B1_PO 5
  185. #define SRST_CORE_B2_PO 6
  186. #define SRST_CORE_B3_PO 7
  187. #define SRST_L2_B 8
  188. #define SRST_ADB_B 9
  189. #define SRST_PD_CORE_B_NIU 10
  190. #define SRST_PDBUS_STRSYS 11
  191. #define SRST_SOCDBG_B 14
  192. #define SRST_CORE_B_DBG 15
  193. #define SRST_DMAC1 18
  194. #define SRST_INTMEM 19
  195. #define SRST_ROM 20
  196. #define SRST_SPDIF8CH 21
  197. #define SRST_I2S8CH 23
  198. #define SRST_MAILBOX 24
  199. #define SRST_I2S2CH 25
  200. #define SRST_EFUSE_256 26
  201. #define SRST_MCU_SYS 28
  202. #define SRST_MCU_PO 29
  203. #define SRST_MCU_NOC 30
  204. #define SRST_EFUSE 31
  205. #define SRST_GPIO0 32
  206. #define SRST_GPIO1 33
  207. #define SRST_GPIO2 34
  208. #define SRST_GPIO3 35
  209. #define SRST_GPIO4 36
  210. #define SRST_PMUGRF 41
  211. #define SRST_I2C0 42
  212. #define SRST_I2C1 43
  213. #define SRST_I2C2 44
  214. #define SRST_I2C3 45
  215. #define SRST_I2C4 46
  216. #define SRST_I2C5 47
  217. #define SRST_DWPWM 48
  218. #define SRST_MMC_PERI 49
  219. #define SRST_PERIPH_MMU 50
  220. #define SRST_GRF 55
  221. #define SRST_PMU 56
  222. #define SRST_PERIPH_AXI 57
  223. #define SRST_PERIPH_AHB 58
  224. #define SRST_PERIPH_APB 59
  225. #define SRST_PERIPH_NIU 60
  226. #define SRST_PDPERI_AHB_ARBI 61
  227. #define SRST_EMEM 62
  228. #define SRST_USB_PERI 63
  229. #define SRST_DMAC2 64
  230. #define SRST_MAC 66
  231. #define SRST_GPS 67
  232. #define SRST_RKPWM 69
  233. #define SRST_USBHOST0 72
  234. #define SRST_HSIC 73
  235. #define SRST_HSIC_AUX 74
  236. #define SRST_HSIC_PHY 75
  237. #define SRST_HSADC 76
  238. #define SRST_NANDC0 77
  239. #define SRST_SFC 79
  240. #define SRST_SPI0 83
  241. #define SRST_SPI1 84
  242. #define SRST_SPI2 85
  243. #define SRST_SARADC 87
  244. #define SRST_PDALIVE_NIU 88
  245. #define SRST_PDPMU_INTMEM 89
  246. #define SRST_PDPMU_NIU 90
  247. #define SRST_SGRF 91
  248. #define SRST_VIO_ARBI 96
  249. #define SRST_RGA_NIU 97
  250. #define SRST_VIO0_NIU_AXI 98
  251. #define SRST_VIO_NIU_AHB 99
  252. #define SRST_LCDC0_AXI 100
  253. #define SRST_LCDC0_AHB 101
  254. #define SRST_LCDC0_DCLK 102
  255. #define SRST_VIP 104
  256. #define SRST_RGA_CORE 105
  257. #define SRST_IEP_AXI 106
  258. #define SRST_IEP_AHB 107
  259. #define SRST_RGA_AXI 108
  260. #define SRST_RGA_AHB 109
  261. #define SRST_ISP 110
  262. #define SRST_EDP_24M 111
  263. #define SRST_VIDEO_AXI 112
  264. #define SRST_VIDEO_AHB 113
  265. #define SRST_MIPIDPHYTX 114
  266. #define SRST_MIPIDSI0 115
  267. #define SRST_MIPIDPHYRX 116
  268. #define SRST_MIPICSI 117
  269. #define SRST_GPU 120
  270. #define SRST_HDMI 121
  271. #define SRST_EDP 122
  272. #define SRST_PMU_PVTM 123
  273. #define SRST_CORE_PVTM 124
  274. #define SRST_GPU_PVTM 125
  275. #define SRST_GPU_SYS 126
  276. #define SRST_GPU_MEM_NIU 127
  277. #define SRST_MMC0 128
  278. #define SRST_SDIO0 129
  279. #define SRST_EMMC 131
  280. #define SRST_USBOTG_AHB 132
  281. #define SRST_USBOTG_PHY 133
  282. #define SRST_USBOTG_CON 134
  283. #define SRST_USBHOST0_AHB 135
  284. #define SRST_USBHOST0_PHY 136
  285. #define SRST_USBHOST0_CON 137
  286. #define SRST_USBOTG_UTMI 138
  287. #define SRST_USBHOST1_UTMI 139
  288. #define SRST_USB_ADP 141
  289. #define SRST_CORESIGHT 144
  290. #define SRST_PD_CORE_AHB_NOC 145
  291. #define SRST_PD_CORE_APB_NOC 146
  292. #define SRST_GIC 148
  293. #define SRST_LCDC_PWM0 149
  294. #define SRST_RGA_H2P_BRG 153
  295. #define SRST_VIDEO 154
  296. #define SRST_GPU_CFG_NIU 157
  297. #define SRST_TSADC 159
  298. #define SRST_DDRPHY0 160
  299. #define SRST_DDRPHY0_APB 161
  300. #define SRST_DDRCTRL0 162
  301. #define SRST_DDRCTRL0_APB 163
  302. #define SRST_VIDEO_NIU 165
  303. #define SRST_VIDEO_NIU_AHB 167
  304. #define SRST_DDRMSCH0 170
  305. #define SRST_PDBUS_AHB 173
  306. #define SRST_CRYPTO 174
  307. #define SRST_UART0 179
  308. #define SRST_UART1 180
  309. #define SRST_UART2 181
  310. #define SRST_UART3 182
  311. #define SRST_UART4 183
  312. #define SRST_SIMC 186
  313. #define SRST_TSP 188
  314. #define SRST_TSP_CLKIN0 189
  315. #define SRST_CORE_L0 192
  316. #define SRST_CORE_L1 193
  317. #define SRST_CORE_L2 194
  318. #define SRST_CORE_L3 195
  319. #define SRST_CORE_L0_PO 195
  320. #define SRST_CORE_L1_PO 197
  321. #define SRST_CORE_L2_PO 198
  322. #define SRST_CORE_L3_PO 199
  323. #define SRST_L2_L 200
  324. #define SRST_ADB_L 201
  325. #define SRST_PD_CORE_L_NIU 202
  326. #define SRST_CCI_SYS 203
  327. #define SRST_CCI_DDR 204
  328. #define SRST_CCI 205
  329. #define SRST_SOCDBG_L 206
  330. #define SRST_CORE_L_DBG 207
  331. #define SRST_CORE_B0_NC 208
  332. #define SRST_CORE_B0_PO_NC 209
  333. #define SRST_L2_B_NC 210
  334. #define SRST_ADB_B_NC 211
  335. #define SRST_PD_CORE_B_NIU_NC 212
  336. #define SRST_PDBUS_STRSYS_NC 213
  337. #define SRST_CORE_L0_NC 214
  338. #define SRST_CORE_L0_PO_NC 215
  339. #define SRST_L2_L_NC 216
  340. #define SRST_ADB_L_NC 217
  341. #define SRST_PD_CORE_L_NIU_NC 218
  342. #define SRST_CCI_SYS_NC 219
  343. #define SRST_CCI_DDR_NC 220
  344. #define SRST_CCI_NC 221
  345. #define SRST_TRACE_NC 222
  346. #define SRST_TIMER00 224
  347. #define SRST_TIMER01 225
  348. #define SRST_TIMER02 226
  349. #define SRST_TIMER03 227
  350. #define SRST_TIMER04 228
  351. #define SRST_TIMER05 229
  352. #define SRST_TIMER10 230
  353. #define SRST_TIMER11 231
  354. #define SRST_TIMER12 232
  355. #define SRST_TIMER13 233
  356. #define SRST_TIMER14 234
  357. #define SRST_TIMER15 235
  358. #define SRST_TIMER0_APB 236
  359. #define SRST_TIMER1_APB 237
  360. #endif