rk3188-cru-common.h 5.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2014 MundoReader S.L.
  4. * Author: Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
  7. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
  8. /* core clocks from */
  9. #define PLL_APLL 1
  10. #define PLL_DPLL 2
  11. #define PLL_CPLL 3
  12. #define PLL_GPLL 4
  13. #define CORE_PERI 5
  14. #define CORE_L2C 6
  15. #define ARMCLK 7
  16. /* sclk gates (special clocks) */
  17. #define SCLK_UART0 64
  18. #define SCLK_UART1 65
  19. #define SCLK_UART2 66
  20. #define SCLK_UART3 67
  21. #define SCLK_MAC 68
  22. #define SCLK_SPI0 69
  23. #define SCLK_SPI1 70
  24. #define SCLK_SARADC 71
  25. #define SCLK_SDMMC 72
  26. #define SCLK_SDIO 73
  27. #define SCLK_EMMC 74
  28. #define SCLK_I2S0 75
  29. #define SCLK_I2S1 76
  30. #define SCLK_I2S2 77
  31. #define SCLK_SPDIF 78
  32. #define SCLK_CIF0 79
  33. #define SCLK_CIF1 80
  34. #define SCLK_OTGPHY0 81
  35. #define SCLK_OTGPHY1 82
  36. #define SCLK_HSADC 83
  37. #define SCLK_TIMER0 84
  38. #define SCLK_TIMER1 85
  39. #define SCLK_TIMER2 86
  40. #define SCLK_TIMER3 87
  41. #define SCLK_TIMER4 88
  42. #define SCLK_TIMER5 89
  43. #define SCLK_TIMER6 90
  44. #define SCLK_JTAG 91
  45. #define SCLK_SMC 92
  46. #define SCLK_TSADC 93
  47. #define DCLK_LCDC0 190
  48. #define DCLK_LCDC1 191
  49. /* aclk gates */
  50. #define ACLK_DMA1 192
  51. #define ACLK_DMA2 193
  52. #define ACLK_GPS 194
  53. #define ACLK_LCDC0 195
  54. #define ACLK_LCDC1 196
  55. #define ACLK_GPU 197
  56. #define ACLK_SMC 198
  57. #define ACLK_CIF 199
  58. #define ACLK_IPP 200
  59. #define ACLK_RGA 201
  60. #define ACLK_CIF0 202
  61. #define ACLK_CPU 203
  62. #define ACLK_PERI 204
  63. /* pclk gates */
  64. #define PCLK_GRF 320
  65. #define PCLK_PMU 321
  66. #define PCLK_TIMER0 322
  67. #define PCLK_TIMER1 323
  68. #define PCLK_TIMER2 324
  69. #define PCLK_TIMER3 325
  70. #define PCLK_PWM01 326
  71. #define PCLK_PWM23 327
  72. #define PCLK_SPI0 328
  73. #define PCLK_SPI1 329
  74. #define PCLK_SARADC 330
  75. #define PCLK_WDT 331
  76. #define PCLK_UART0 332
  77. #define PCLK_UART1 333
  78. #define PCLK_UART2 334
  79. #define PCLK_UART3 335
  80. #define PCLK_I2C0 336
  81. #define PCLK_I2C1 337
  82. #define PCLK_I2C2 338
  83. #define PCLK_I2C3 339
  84. #define PCLK_I2C4 340
  85. #define PCLK_GPIO0 341
  86. #define PCLK_GPIO1 342
  87. #define PCLK_GPIO2 343
  88. #define PCLK_GPIO3 344
  89. #define PCLK_GPIO4 345
  90. #define PCLK_GPIO6 346
  91. #define PCLK_EFUSE 347
  92. #define PCLK_TZPC 348
  93. #define PCLK_TSADC 349
  94. #define PCLK_CPU 350
  95. #define PCLK_PERI 351
  96. #define PCLK_DDRUPCTL 352
  97. #define PCLK_PUBL 353
  98. /* hclk gates */
  99. #define HCLK_SDMMC 448
  100. #define HCLK_SDIO 449
  101. #define HCLK_EMMC 450
  102. #define HCLK_OTG0 451
  103. #define HCLK_EMAC 452
  104. #define HCLK_SPDIF 453
  105. #define HCLK_I2S0 454
  106. #define HCLK_I2S1 455
  107. #define HCLK_I2S2 456
  108. #define HCLK_OTG1 457
  109. #define HCLK_HSIC 458
  110. #define HCLK_HSADC 459
  111. #define HCLK_PIDF 460
  112. #define HCLK_LCDC0 461
  113. #define HCLK_LCDC1 462
  114. #define HCLK_ROM 463
  115. #define HCLK_CIF0 464
  116. #define HCLK_IPP 465
  117. #define HCLK_RGA 466
  118. #define HCLK_NANDC0 467
  119. #define HCLK_CPU 468
  120. #define HCLK_PERI 469
  121. #define CLK_NR_CLKS (HCLK_PERI + 1)
  122. /* soft-reset indices */
  123. #define SRST_MCORE 2
  124. #define SRST_CORE0 3
  125. #define SRST_CORE1 4
  126. #define SRST_MCORE_DBG 7
  127. #define SRST_CORE0_DBG 8
  128. #define SRST_CORE1_DBG 9
  129. #define SRST_CORE0_WDT 12
  130. #define SRST_CORE1_WDT 13
  131. #define SRST_STRC_SYS 14
  132. #define SRST_L2C 15
  133. #define SRST_CPU_AHB 17
  134. #define SRST_AHB2APB 19
  135. #define SRST_DMA1 20
  136. #define SRST_INTMEM 21
  137. #define SRST_ROM 22
  138. #define SRST_SPDIF 26
  139. #define SRST_TIMER0 27
  140. #define SRST_TIMER1 28
  141. #define SRST_EFUSE 30
  142. #define SRST_GPIO0 32
  143. #define SRST_GPIO1 33
  144. #define SRST_GPIO2 34
  145. #define SRST_GPIO3 35
  146. #define SRST_UART0 39
  147. #define SRST_UART1 40
  148. #define SRST_UART2 41
  149. #define SRST_UART3 42
  150. #define SRST_I2C0 43
  151. #define SRST_I2C1 44
  152. #define SRST_I2C2 45
  153. #define SRST_I2C3 46
  154. #define SRST_I2C4 47
  155. #define SRST_PWM0 48
  156. #define SRST_PWM1 49
  157. #define SRST_DAP_PO 50
  158. #define SRST_DAP 51
  159. #define SRST_DAP_SYS 52
  160. #define SRST_TPIU_ATB 53
  161. #define SRST_PMU_APB 54
  162. #define SRST_GRF 55
  163. #define SRST_PMU 56
  164. #define SRST_PERI_AXI 57
  165. #define SRST_PERI_AHB 58
  166. #define SRST_PERI_APB 59
  167. #define SRST_PERI_NIU 60
  168. #define SRST_CPU_PERI 61
  169. #define SRST_EMEM_PERI 62
  170. #define SRST_USB_PERI 63
  171. #define SRST_DMA2 64
  172. #define SRST_SMC 65
  173. #define SRST_MAC 66
  174. #define SRST_NANC0 68
  175. #define SRST_USBOTG0 69
  176. #define SRST_USBPHY0 70
  177. #define SRST_OTGC0 71
  178. #define SRST_USBOTG1 72
  179. #define SRST_USBPHY1 73
  180. #define SRST_OTGC1 74
  181. #define SRST_HSADC 76
  182. #define SRST_PIDFILTER 77
  183. #define SRST_DDR_MSCH 79
  184. #define SRST_TZPC 80
  185. #define SRST_SDMMC 81
  186. #define SRST_SDIO 82
  187. #define SRST_EMMC 83
  188. #define SRST_SPI0 84
  189. #define SRST_SPI1 85
  190. #define SRST_WDT 86
  191. #define SRST_SARADC 87
  192. #define SRST_DDRPHY 88
  193. #define SRST_DDRPHY_APB 89
  194. #define SRST_DDRCTL 90
  195. #define SRST_DDRCTL_APB 91
  196. #define SRST_DDRPUB 93
  197. #define SRST_VIO0_AXI 98
  198. #define SRST_VIO0_AHB 99
  199. #define SRST_LCDC0_AXI 100
  200. #define SRST_LCDC0_AHB 101
  201. #define SRST_LCDC0_DCLK 102
  202. #define SRST_LCDC1_AXI 103
  203. #define SRST_LCDC1_AHB 104
  204. #define SRST_LCDC1_DCLK 105
  205. #define SRST_IPP_AXI 106
  206. #define SRST_IPP_AHB 107
  207. #define SRST_RGA_AXI 108
  208. #define SRST_RGA_AHB 109
  209. #define SRST_CIF0 110
  210. #define SRST_VCODEC_AXI 112
  211. #define SRST_VCODEC_AHB 113
  212. #define SRST_VIO1_AXI 114
  213. #define SRST_VCODEC_CPU 115
  214. #define SRST_VCODEC_NIU 116
  215. #define SRST_GPU 120
  216. #define SRST_GPU_NIU 122
  217. #define SRST_TFUN_ATB 125
  218. #define SRST_TFUN_APB 126
  219. #define SRST_CTI4_APB 127
  220. #define SRST_TPIU_APB 128
  221. #define SRST_TRACE 129
  222. #define SRST_CORE_DBG 130
  223. #define SRST_DBG_APB 131
  224. #define SRST_CTI0 132
  225. #define SRST_CTI0_APB 133
  226. #define SRST_CTI1 134
  227. #define SRST_CTI1_APB 135
  228. #define SRST_PTM_CORE0 136
  229. #define SRST_PTM_CORE1 137
  230. #define SRST_PTM0 138
  231. #define SRST_PTM0_ATB 139
  232. #define SRST_PTM1 140
  233. #define SRST_PTM1_ATB 141
  234. #define SRST_CTM 142
  235. #define SRST_TS 143
  236. #endif