rk3036-cru.h 4.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2014 MundoReader S.L.
  4. * Author: Heiko Stuebner <heiko@sntech.de>
  5. */
  6. #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
  7. #define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
  8. /* core clocks */
  9. #define PLL_APLL 1
  10. #define PLL_DPLL 2
  11. #define PLL_GPLL 3
  12. #define ARMCLK 4
  13. /* sclk gates (special clocks) */
  14. #define SCLK_GPU 64
  15. #define SCLK_SPI 65
  16. #define SCLK_SDMMC 68
  17. #define SCLK_SDIO 69
  18. #define SCLK_EMMC 71
  19. #define SCLK_NANDC 76
  20. #define SCLK_UART0 77
  21. #define SCLK_UART1 78
  22. #define SCLK_UART2 79
  23. #define SCLK_I2S 82
  24. #define SCLK_SPDIF 83
  25. #define SCLK_TIMER0 85
  26. #define SCLK_TIMER1 86
  27. #define SCLK_TIMER2 87
  28. #define SCLK_TIMER3 88
  29. #define SCLK_OTGPHY0 93
  30. #define SCLK_LCDC 100
  31. #define SCLK_HDMI 109
  32. #define SCLK_HEVC 111
  33. #define SCLK_I2S_OUT 113
  34. #define SCLK_SDMMC_DRV 114
  35. #define SCLK_SDIO_DRV 115
  36. #define SCLK_EMMC_DRV 117
  37. #define SCLK_SDMMC_SAMPLE 118
  38. #define SCLK_SDIO_SAMPLE 119
  39. #define SCLK_EMMC_SAMPLE 121
  40. #define SCLK_PVTM_CORE 123
  41. #define SCLK_PVTM_GPU 124
  42. #define SCLK_PVTM_VIDEO 125
  43. #define SCLK_MAC 151
  44. #define SCLK_MACREF 152
  45. #define SCLK_SFC 160
  46. #define DCLK_LCDC 190
  47. /* aclk gates */
  48. #define ACLK_DMAC2 194
  49. #define ACLK_LCDC 197
  50. #define ACLK_VIO 203
  51. #define ACLK_VCODEC 208
  52. #define ACLK_CPU 209
  53. #define ACLK_PERI 210
  54. /* pclk gates */
  55. #define PCLK_GPIO0 320
  56. #define PCLK_GPIO1 321
  57. #define PCLK_GPIO2 322
  58. #define PCLK_GRF 329
  59. #define PCLK_I2C0 332
  60. #define PCLK_I2C1 333
  61. #define PCLK_I2C2 334
  62. #define PCLK_SPI 338
  63. #define PCLK_UART0 341
  64. #define PCLK_UART1 342
  65. #define PCLK_UART2 343
  66. #define PCLK_PWM 350
  67. #define PCLK_TIMER 353
  68. #define PCLK_HDMI 360
  69. #define PCLK_CPU 362
  70. #define PCLK_PERI 363
  71. #define PCLK_DDRUPCTL 364
  72. #define PCLK_WDT 368
  73. /* hclk gates */
  74. #define HCLK_OTG0 449
  75. #define HCLK_OTG1 450
  76. #define HCLK_NANDC 453
  77. #define HCLK_SDMMC 456
  78. #define HCLK_SDIO 457
  79. #define HCLK_EMMC 459
  80. #define HCLK_I2S 462
  81. #define HCLK_LCDC 465
  82. #define HCLK_ROM 467
  83. #define HCLK_VIO_BUS 472
  84. #define HCLK_VCODEC 476
  85. #define HCLK_CPU 477
  86. #define HCLK_PERI 478
  87. #define CLK_NR_CLKS (HCLK_PERI + 1)
  88. /* soft-reset indices */
  89. #define SRST_CORE0 0
  90. #define SRST_CORE1 1
  91. #define SRST_CORE0_DBG 4
  92. #define SRST_CORE1_DBG 5
  93. #define SRST_CORE0_POR 8
  94. #define SRST_CORE1_POR 9
  95. #define SRST_L2C 12
  96. #define SRST_TOPDBG 13
  97. #define SRST_STRC_SYS_A 14
  98. #define SRST_PD_CORE_NIU 15
  99. #define SRST_TIMER2 16
  100. #define SRST_CPUSYS_H 17
  101. #define SRST_AHB2APB_H 19
  102. #define SRST_TIMER3 20
  103. #define SRST_INTMEM 21
  104. #define SRST_ROM 22
  105. #define SRST_PERI_NIU 23
  106. #define SRST_I2S 24
  107. #define SRST_DDR_PLL 25
  108. #define SRST_GPU_DLL 26
  109. #define SRST_TIMER0 27
  110. #define SRST_TIMER1 28
  111. #define SRST_CORE_DLL 29
  112. #define SRST_EFUSE_P 30
  113. #define SRST_ACODEC_P 31
  114. #define SRST_GPIO0 32
  115. #define SRST_GPIO1 33
  116. #define SRST_GPIO2 34
  117. #define SRST_UART0 39
  118. #define SRST_UART1 40
  119. #define SRST_UART2 41
  120. #define SRST_I2C0 43
  121. #define SRST_I2C1 44
  122. #define SRST_I2C2 45
  123. #define SRST_SFC 47
  124. #define SRST_PWM0 48
  125. #define SRST_DAP 51
  126. #define SRST_DAP_SYS 52
  127. #define SRST_GRF 55
  128. #define SRST_PERIPHSYS_A 57
  129. #define SRST_PERIPHSYS_H 58
  130. #define SRST_PERIPHSYS_P 59
  131. #define SRST_CPU_PERI 61
  132. #define SRST_EMEM_PERI 62
  133. #define SRST_USB_PERI 63
  134. #define SRST_DMA2 64
  135. #define SRST_MAC 66
  136. #define SRST_NANDC 68
  137. #define SRST_USBOTG0 69
  138. #define SRST_OTGC0 71
  139. #define SRST_USBOTG1 72
  140. #define SRST_OTGC1 74
  141. #define SRST_DDRMSCH 79
  142. #define SRST_MMC0 81
  143. #define SRST_SDIO 82
  144. #define SRST_EMMC 83
  145. #define SRST_SPI0 84
  146. #define SRST_WDT 86
  147. #define SRST_DDRPHY 88
  148. #define SRST_DDRPHY_P 89
  149. #define SRST_DDRCTRL 90
  150. #define SRST_DDRCTRL_P 91
  151. #define SRST_HDMI_P 96
  152. #define SRST_VIO_BUS_H 99
  153. #define SRST_UTMI0 103
  154. #define SRST_UTMI1 104
  155. #define SRST_USBPOR 105
  156. #define SRST_VCODEC_A 112
  157. #define SRST_VCODEC_H 113
  158. #define SRST_VIO1_A 114
  159. #define SRST_HEVC 115
  160. #define SRST_VCODEC_NIU_A 116
  161. #define SRST_LCDC1_A 117
  162. #define SRST_LCDC1_H 118
  163. #define SRST_LCDC1_D 119
  164. #define SRST_GPU 120
  165. #define SRST_GPU_NIU_A 122
  166. #define SRST_DBG_P 131
  167. #endif