r8a7790-clock.h 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Copyright 2013 Ideas On Board SPRL
  4. */
  5. #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
  6. #define __DT_BINDINGS_CLOCK_R8A7790_H__
  7. /* CPG */
  8. #define R8A7790_CLK_MAIN 0
  9. #define R8A7790_CLK_PLL0 1
  10. #define R8A7790_CLK_PLL1 2
  11. #define R8A7790_CLK_PLL3 3
  12. #define R8A7790_CLK_LB 4
  13. #define R8A7790_CLK_QSPI 5
  14. #define R8A7790_CLK_SDH 6
  15. #define R8A7790_CLK_SD0 7
  16. #define R8A7790_CLK_SD1 8
  17. #define R8A7790_CLK_Z 9
  18. #define R8A7790_CLK_RCAN 10
  19. #define R8A7790_CLK_ADSP 11
  20. /* MSTP0 */
  21. #define R8A7790_CLK_MSIOF0 0
  22. /* MSTP1 */
  23. #define R8A7790_CLK_VCP1 0
  24. #define R8A7790_CLK_VCP0 1
  25. #define R8A7790_CLK_VPC1 2
  26. #define R8A7790_CLK_VPC0 3
  27. #define R8A7790_CLK_JPU 6
  28. #define R8A7790_CLK_SSP1 9
  29. #define R8A7790_CLK_TMU1 11
  30. #define R8A7790_CLK_3DG 12
  31. #define R8A7790_CLK_2DDMAC 15
  32. #define R8A7790_CLK_FDP1_2 17
  33. #define R8A7790_CLK_FDP1_1 18
  34. #define R8A7790_CLK_FDP1_0 19
  35. #define R8A7790_CLK_TMU3 21
  36. #define R8A7790_CLK_TMU2 22
  37. #define R8A7790_CLK_CMT0 24
  38. #define R8A7790_CLK_TMU0 25
  39. #define R8A7790_CLK_VSP1_DU1 27
  40. #define R8A7790_CLK_VSP1_DU0 28
  41. #define R8A7790_CLK_VSP1_R 30
  42. #define R8A7790_CLK_VSP1_S 31
  43. /* MSTP2 */
  44. #define R8A7790_CLK_SCIFA2 2
  45. #define R8A7790_CLK_SCIFA1 3
  46. #define R8A7790_CLK_SCIFA0 4
  47. #define R8A7790_CLK_MSIOF2 5
  48. #define R8A7790_CLK_SCIFB0 6
  49. #define R8A7790_CLK_SCIFB1 7
  50. #define R8A7790_CLK_MSIOF1 8
  51. #define R8A7790_CLK_MSIOF3 15
  52. #define R8A7790_CLK_SCIFB2 16
  53. #define R8A7790_CLK_SYS_DMAC1 18
  54. #define R8A7790_CLK_SYS_DMAC0 19
  55. /* MSTP3 */
  56. #define R8A7790_CLK_IIC2 0
  57. #define R8A7790_CLK_TPU0 4
  58. #define R8A7790_CLK_MMCIF1 5
  59. #define R8A7790_CLK_SCIF2 10
  60. #define R8A7790_CLK_SDHI3 11
  61. #define R8A7790_CLK_SDHI2 12
  62. #define R8A7790_CLK_SDHI1 13
  63. #define R8A7790_CLK_SDHI0 14
  64. #define R8A7790_CLK_MMCIF0 15
  65. #define R8A7790_CLK_IIC0 18
  66. #define R8A7790_CLK_PCIEC 19
  67. #define R8A7790_CLK_IIC1 23
  68. #define R8A7790_CLK_SSUSB 28
  69. #define R8A7790_CLK_CMT1 29
  70. #define R8A7790_CLK_USBDMAC0 30
  71. #define R8A7790_CLK_USBDMAC1 31
  72. /* MSTP4 */
  73. #define R8A7790_CLK_IRQC 7
  74. #define R8A7790_CLK_INTC_SYS 8
  75. /* MSTP5 */
  76. #define R8A7790_CLK_AUDIO_DMAC1 1
  77. #define R8A7790_CLK_AUDIO_DMAC0 2
  78. #define R8A7790_CLK_ADSP_MOD 6
  79. #define R8A7790_CLK_THERMAL 22
  80. #define R8A7790_CLK_PWM 23
  81. /* MSTP7 */
  82. #define R8A7790_CLK_EHCI 3
  83. #define R8A7790_CLK_HSUSB 4
  84. #define R8A7790_CLK_HSCIF1 16
  85. #define R8A7790_CLK_HSCIF0 17
  86. #define R8A7790_CLK_SCIF1 20
  87. #define R8A7790_CLK_SCIF0 21
  88. #define R8A7790_CLK_DU2 22
  89. #define R8A7790_CLK_DU1 23
  90. #define R8A7790_CLK_DU0 24
  91. #define R8A7790_CLK_LVDS1 25
  92. #define R8A7790_CLK_LVDS0 26
  93. /* MSTP8 */
  94. #define R8A7790_CLK_MLB 2
  95. #define R8A7790_CLK_VIN3 8
  96. #define R8A7790_CLK_VIN2 9
  97. #define R8A7790_CLK_VIN1 10
  98. #define R8A7790_CLK_VIN0 11
  99. #define R8A7790_CLK_ETHERAVB 12
  100. #define R8A7790_CLK_ETHER 13
  101. #define R8A7790_CLK_SATA1 14
  102. #define R8A7790_CLK_SATA0 15
  103. /* MSTP9 */
  104. #define R8A7790_CLK_GPIO5 7
  105. #define R8A7790_CLK_GPIO4 8
  106. #define R8A7790_CLK_GPIO3 9
  107. #define R8A7790_CLK_GPIO2 10
  108. #define R8A7790_CLK_GPIO1 11
  109. #define R8A7790_CLK_GPIO0 12
  110. #define R8A7790_CLK_RCAN1 15
  111. #define R8A7790_CLK_RCAN0 16
  112. #define R8A7790_CLK_QSPI_MOD 17
  113. #define R8A7790_CLK_IICDVFS 26
  114. #define R8A7790_CLK_I2C3 28
  115. #define R8A7790_CLK_I2C2 29
  116. #define R8A7790_CLK_I2C1 30
  117. #define R8A7790_CLK_I2C0 31
  118. /* MSTP10 */
  119. #define R8A7790_CLK_SSI_ALL 5
  120. #define R8A7790_CLK_SSI9 6
  121. #define R8A7790_CLK_SSI8 7
  122. #define R8A7790_CLK_SSI7 8
  123. #define R8A7790_CLK_SSI6 9
  124. #define R8A7790_CLK_SSI5 10
  125. #define R8A7790_CLK_SSI4 11
  126. #define R8A7790_CLK_SSI3 12
  127. #define R8A7790_CLK_SSI2 13
  128. #define R8A7790_CLK_SSI1 14
  129. #define R8A7790_CLK_SSI0 15
  130. #define R8A7790_CLK_SCU_ALL 17
  131. #define R8A7790_CLK_SCU_DVC1 18
  132. #define R8A7790_CLK_SCU_DVC0 19
  133. #define R8A7790_CLK_SCU_CTU1_MIX1 20
  134. #define R8A7790_CLK_SCU_CTU0_MIX0 21
  135. #define R8A7790_CLK_SCU_SRC9 22
  136. #define R8A7790_CLK_SCU_SRC8 23
  137. #define R8A7790_CLK_SCU_SRC7 24
  138. #define R8A7790_CLK_SCU_SRC6 25
  139. #define R8A7790_CLK_SCU_SRC5 26
  140. #define R8A7790_CLK_SCU_SRC4 27
  141. #define R8A7790_CLK_SCU_SRC3 28
  142. #define R8A7790_CLK_SCU_SRC2 29
  143. #define R8A7790_CLK_SCU_SRC1 30
  144. #define R8A7790_CLK_SCU_SRC0 31
  145. #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */