cortina.h 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Cortina PHY drivers
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. */
  7. #ifndef _CORTINA_H_
  8. #define _CORTINA_H_
  9. #define VILLA_GLOBAL_CHIP_ID_LSB 0x000
  10. #define VILLA_GLOBAL_CHIP_ID_MSB 0x001
  11. #define VILLA_GLOBAL_BIST_CONTROL 0x002
  12. #define VILLA_GLOBAL_BIST_STATUS 0x003
  13. #define VILLA_GLOBAL_LINE_SOFT_RESET 0x007
  14. #define VILLA_GLOBAL_HOST_SOFT_RESET 0x008
  15. #define VILLA_GLOBAL_DWNLD_CHECKSUM_CTRL 0x00A
  16. #define VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS 0x00B
  17. #define VILLA_GLOBAL_MSEQCLKCTRL 0x00E
  18. #define VILLA_MSEQ_OPTIONS 0x1D0
  19. #define VILLA_MSEQ_PC 0x1D3
  20. #define VILLA_MSEQ_BANKSELECT 0x1DF
  21. #define VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT 0x2DB
  22. #define VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT 0x36E
  23. #define VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER 0x403
  24. #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPA 0x404
  25. #define VILLA_LINE_SDS_COMMON_SRX0_RX_CPB 0x405
  26. #define VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL 0x369
  27. #define VILLA_MSEQ_ENABLE_MSB 0x194
  28. #define VILLA_MSEQ_SPARE21_LSB 0x226
  29. #define VILLA_MSEQ_RESET_COUNT_LSB 0x1E0
  30. #define VILLA_MSEQ_SPARE12_MSB 0x215
  31. #define VILLA_MSEQ_SPARE2_LSB 0x200
  32. #define VILLA_MSEQ_SPARE7_LSB 0x20A
  33. #define VILLA_MSEQ_SPARE9_LSB 0x20E
  34. #define VILLA_MSEQ_SPARE3_LSB 0x202
  35. #define VILLA_MSEQ_SPARE3_MSB 0x203
  36. #define VILLA_MSEQ_SPARE8_LSB 0x20C
  37. #define VILLA_MSEQ_SPARE8_MSB 0x20D
  38. #define VILLA_MSEQ_COEF8_FFE0_LSB 0x1E2
  39. #define VILLA_MSEQ_COEF8_FFE1_LSB 0x1E4
  40. #define VILLA_MSEQ_COEF8_FFE2_LSB 0x1E6
  41. #define VILLA_MSEQ_COEF8_FFE3_LSB 0x1E8
  42. #define VILLA_MSEQ_COEF8_FFE4_LSB 0x1EA
  43. #define VILLA_MSEQ_COEF8_FFE5_LSB 0x1EC
  44. #define VILLA_MSEQ_COEF8_DFE0_LSB 0x1F0
  45. #define VILLA_MSEQ_COEF8_DFE0N_LSB 0x1EE
  46. #define VILLA_MSEQ_COEF8_DFE1_LSB 0x1F2
  47. #define VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK 0x2E2
  48. #define VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB 0x360
  49. #define VILLA_MSEQ_POWER_DOWN_LSB 0x198
  50. #define VILLA_MSEQ_POWER_DOWN_MSB 0x199
  51. #define VILLA_MSEQ_CAL_RX_SLICER 0x1B8
  52. #define VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB 0x365
  53. #define VILLA_MSEQ_COEF_INIT_SEL 0x1AE
  54. #define VILLA_DSP_SDS_DSP_PRECODEDINITFFE21 0x26A
  55. #define VILLA_MSEQ_SERDES_PARAM_LSB 0x195
  56. #define VILLA_MSEQ_SPARE25_LSB 0x22E
  57. #define VILLA_MSEQ_SPARE23_LSB 0x22A
  58. #define VILLA_MSEQ_CAL_RX_DFE_EQ 0x1BA
  59. #define VILLA_GLOBAL_VILLA2_COMPATIBLE 0x030
  60. #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x812
  61. #define VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x813
  62. #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x427
  63. #define VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x428
  64. /* Cortina CS4223 */
  65. #define CS4223_EEPROM_STATUS 0x5001
  66. #define CS4223_EEPROM_FIRMWARE_LOADDONE 0x1
  67. #define mseq_edc_bist_done (0x1<<0)
  68. #define mseq_edc_bist_fail (0x1<<8)
  69. struct cortina_reg_config {
  70. unsigned short reg_addr;
  71. unsigned short reg_value;
  72. };
  73. #endif