xtfpga.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007-2013 Tensilica, Inc.
  4. * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #include <asm/arch/core.h>
  9. #include <asm/addrspace.h>
  10. #include <asm/config.h>
  11. /*
  12. * The 'xtfpga' board describes a set of very similar boards with only minimal
  13. * differences.
  14. */
  15. /*=====================*/
  16. /* Board and Processor */
  17. /*=====================*/
  18. #define CONFIG_XTFPGA
  19. /* FPGA CPU freq after init */
  20. #define CONFIG_SYS_CLK_FREQ (gd->cpu_clk)
  21. /*===================*/
  22. /* RAM Layout */
  23. /*===================*/
  24. #if XCHAL_HAVE_PTP_MMU
  25. #define CONFIG_SYS_MEMORY_BASE \
  26. (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
  27. #define CONFIG_SYS_IO_BASE 0xf0000000
  28. #else
  29. #define CONFIG_SYS_MEMORY_BASE 0x60000000
  30. #define CONFIG_SYS_IO_BASE 0x90000000
  31. #define CONFIG_MAX_MEM_MAPPED 0x10000000
  32. #endif
  33. /* Onboard RAM sizes:
  34. *
  35. * LX60 0x04000000 64 MB
  36. * LX110 0x03000000 48 MB
  37. * LX200 0x06000000 96 MB
  38. * ML605 0x18000000 384 MB
  39. * KC705 0x38000000 896 MB
  40. *
  41. * noMMU configurations can only see first 256MB of onboard memory.
  42. */
  43. #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
  44. #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
  45. #else
  46. #define CONFIG_SYS_SDRAM_SIZE 0x10000000
  47. #endif
  48. #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
  49. /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
  50. #ifdef CONFIG_XTFPGA_LX60
  51. # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
  52. #else
  53. # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
  54. #endif
  55. #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */
  56. /* Linux boot param area in RAM (used only when booting linux) */
  57. #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10)
  58. /* Memory test is destructive so default must not overlap vectors or U-Boot*/
  59. /* Load address for stand-alone applications.
  60. * MEMADDR cannot be used here, because the definition needs to be
  61. * a plain number as it's used as -Ttext argument for ld in standalone
  62. * example makefile.
  63. * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
  64. */
  65. #if XCHAL_HAVE_PTP_MMU
  66. #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
  67. #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000
  68. #else
  69. #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000
  70. #endif
  71. #else
  72. #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000
  73. #endif
  74. #if defined(CONFIG_MAX_MEM_MAPPED) && \
  75. CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
  76. #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED
  77. #else
  78. #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
  79. #endif
  80. #define XTENSA_SYS_TEXT_ADDR \
  81. (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
  82. /* Used by tftpboot; env var 'loadaddr' */
  83. #define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000)
  84. /*==============================*/
  85. /* U-Boot general configuration */
  86. /*==============================*/
  87. #define CONFIG_BOARD_POSTCLK_INIT
  88. #define CONFIG_BOOTFILE "uImage"
  89. /* Console I/O Buffer Size */
  90. #define CONFIG_SYS_CBSIZE 1024
  91. /* Boot Argument Buffer Size */
  92. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  93. /*==============================*/
  94. /* U-Boot autoboot configuration */
  95. /*==============================*/
  96. /*=========================================*/
  97. /* FPGA Registers (board info and control) */
  98. /*=========================================*/
  99. /*
  100. * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
  101. * releases may not provide any/all of these registers or at these offsets.
  102. * Some of the FPGA registers are broken down into bitfields described by
  103. * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
  104. */
  105. /* Date of FPGA bitstream build in binary coded decimal (BCD) */
  106. #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
  107. #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */
  108. #define FPGAREG_MTH_WIDTH 8
  109. #define FPGAREG_MTH_MASK 0xFF000000
  110. #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */
  111. #define FPGAREG_DAY_WIDTH 8
  112. #define FPGAREG_DAY_MASK 0x00FF0000
  113. #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/
  114. #define FPGAREG_YEAR_WIDTH 16
  115. #define FPGAREG_YEAR_MASK 0x0000FFFF
  116. /* FPGA core clock frequency in Hz (also input to UART) */
  117. #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
  118. /*
  119. * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
  120. * Bits 0..5 set the lower 6 bits of the default ethernet MAC.
  121. * Bit 6 is reserved for future use by Tensilica.
  122. * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
  123. * the base of flash * (when on/1) or to the base of RAM (when off/0).
  124. */
  125. #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
  126. #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
  127. #define FPGAREG_MAC_WIDTH 6
  128. #define FPGAREG_MAC_MASK 0x3f
  129. #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
  130. #define FPGAREG_BOOT_WIDTH 1
  131. #define FPGAREG_BOOT_MASK 0x80
  132. #define FPGAREG_BOOT_RAM 0
  133. #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
  134. /* Force hard reset of board by writing a code to this register */
  135. #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
  136. #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
  137. /*====================*/
  138. /* Serial Driver Info */
  139. /*====================*/
  140. #define CONFIG_SYS_NS16550_SERIAL
  141. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  142. #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
  143. /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
  144. #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
  145. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  146. /*======================*/
  147. /* Ethernet Driver Info */
  148. /*======================*/
  149. #define CONFIG_ETHBASE 00:50:C2:13:6f:00
  150. #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
  151. #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
  152. /*=====================*/
  153. /* Flash & Environment */
  154. /*=====================*/
  155. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  156. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  157. #ifdef CONFIG_XTFPGA_LX60
  158. # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
  159. # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */
  160. # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
  161. # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
  162. # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  163. #elif defined(CONFIG_XTFPGA_KC705)
  164. # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
  165. # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
  166. # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
  167. # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
  168. # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000)
  169. #else
  170. # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
  171. # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
  172. # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
  173. # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
  174. # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  175. #endif
  176. #define CONFIG_SYS_MAX_FLASH_SECT \
  177. (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
  178. CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
  179. /*
  180. * Put environment in top block (64kB)
  181. * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
  182. */
  183. /* print 'E' for empty sector on flinfo */
  184. #define CONFIG_SYS_FLASH_EMPTY_INFO
  185. #endif /* __CONFIG_H */