xpedite520x.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008 Extreme Engineering Solutions, Inc.
  4. * Copyright 2004-2008 Freescale Semiconductor, Inc.
  5. */
  6. /*
  7. * xpedite520x board configuration file
  8. */
  9. #ifndef __CONFIG_H
  10. #define __CONFIG_H
  11. /*
  12. * High Level Configuration Options
  13. */
  14. #define CONFIG_SYS_BOARD_NAME "XPedite5200"
  15. #define CONFIG_SYS_FORM_PMC_XMC 1
  16. #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
  17. #define CONFIG_PCI1 1 /* PCI controller 1 */
  18. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  19. #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
  20. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  21. /*
  22. * DDR config
  23. */
  24. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  25. #define CONFIG_DDR_SPD
  26. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  27. #define SPD_EEPROM_ADDRESS 0x54
  28. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  29. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  30. #define CONFIG_DDR_ECC
  31. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  32. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  33. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  34. #define CONFIG_VERY_BIG_RAM
  35. #define CONFIG_SYS_CLK_FREQ 66666666
  36. /*
  37. * These can be toggled for performance analysis, otherwise use default.
  38. */
  39. #define CONFIG_L2_CACHE /* toggle L2 cache */
  40. #define CONFIG_BTB /* toggle branch predition */
  41. #define CONFIG_ENABLE_36BIT_PHYS 1
  42. #define CONFIG_SYS_CCSRBAR 0xef000000
  43. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  44. /*
  45. * Diagnostics
  46. */
  47. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  48. CONFIG_SYS_POST_I2C)
  49. #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
  50. CONFIG_SYS_I2C_EEPROM_ADDR, \
  51. CONFIG_SYS_I2C_PCA953X_ADDR0, \
  52. CONFIG_SYS_I2C_PCA953X_ADDR1, \
  53. CONFIG_SYS_I2C_RTC_ADDR}
  54. /*
  55. * Memory map
  56. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  57. * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
  58. * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
  59. * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
  60. * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
  61. * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
  62. * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
  63. * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
  64. */
  65. #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
  66. /*
  67. * NAND flash configuration
  68. */
  69. #define CONFIG_SYS_NAND_BASE 0xef800000
  70. #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
  71. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  72. #define CONFIG_NAND_ACTL
  73. #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
  74. #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
  75. #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
  76. #define CONFIG_SYS_NAND_ACTL_DELAY 25
  77. /*
  78. * NOR flash configuration
  79. */
  80. #define CONFIG_SYS_FLASH_BASE 0xfc000000
  81. #define CONFIG_SYS_FLASH_BASE2 0xf8000000
  82. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
  83. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  84. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  85. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  86. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  87. #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
  88. {0xfbf40000, 0xc0000} }
  89. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  90. /*
  91. * Chip select configuration
  92. */
  93. /* NOR Flash 0 on CS0 */
  94. #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
  95. BR_PS_16 | \
  96. BR_V)
  97. #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
  98. OR_GPCM_ACS_DIV4 | \
  99. OR_GPCM_SCY_8)
  100. /* NOR Flash 1 on CS1 */
  101. #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
  102. BR_PS_16 | \
  103. BR_V)
  104. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  105. /* NAND flash on CS2 */
  106. #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
  107. BR_PS_8 | \
  108. BR_V)
  109. /* NAND flash on CS2 */
  110. #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
  111. OR_GPCM_BCTLD | \
  112. OR_GPCM_CSNT | \
  113. OR_GPCM_ACS_DIV4 | \
  114. OR_GPCM_SCY_4 | \
  115. OR_GPCM_TRLX | \
  116. OR_GPCM_EHTR)
  117. /* NAND flash on CS3 */
  118. #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
  119. BR_PS_8 | \
  120. BR_V)
  121. #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
  122. /*
  123. * Use L1 as initial stack
  124. */
  125. #define CONFIG_SYS_INIT_RAM_LOCK 1
  126. #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
  127. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
  128. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  129. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  130. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
  131. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  132. /*
  133. * Serial Port
  134. */
  135. #define CONFIG_SYS_NS16550_SERIAL
  136. #define CONFIG_SYS_NS16550_REG_SIZE 1
  137. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  138. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  139. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  140. #define CONFIG_SYS_BAUDRATE_TABLE \
  141. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  142. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  143. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  144. /*
  145. * I2C
  146. */
  147. #define CONFIG_SYS_I2C
  148. #define CONFIG_SYS_I2C_FSL
  149. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  150. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  151. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  152. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  153. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  154. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  155. /* I2C EEPROM */
  156. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  157. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  158. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
  159. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
  160. /* I2C RTC */
  161. #define CONFIG_RTC_M41T11 1
  162. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  163. #define CONFIG_SYS_M41T11_BASE_YEAR 2000
  164. /* GPIO */
  165. #define CONFIG_PCA953X
  166. #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
  167. #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
  168. #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
  169. /* PCA957 @ 0x18 */
  170. #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
  171. #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
  172. #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
  173. #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
  174. #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
  175. #define CONFIG_SYS_PCA953X_NVM_WP 0x20
  176. #define CONFIG_SYS_PCA953X_MONARCH 0x40
  177. #define CONFIG_SYS_PCA953X_EREADY 0x80
  178. /* PCA957 @ 0x19 */
  179. #define CONFIG_SYS_PCA953X_P14_IO0 0x01
  180. #define CONFIG_SYS_PCA953X_P14_IO1 0x02
  181. #define CONFIG_SYS_PCA953X_P14_IO2 0x04
  182. #define CONFIG_SYS_PCA953X_P14_IO3 0x08
  183. #define CONFIG_SYS_PCA953X_P14_IO4 0x10
  184. #define CONFIG_SYS_PCA953X_P14_IO5 0x20
  185. #define CONFIG_SYS_PCA953X_P14_IO6 0x40
  186. #define CONFIG_SYS_PCA953X_P14_IO7 0x80
  187. /* 12-bit ADC used to measure CPU diode */
  188. #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
  189. /*
  190. * General PCI
  191. * Memory space is mapped 1-1, but I/O space must start from 0.
  192. */
  193. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  194. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  195. #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
  196. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  197. #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
  198. #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
  199. /*
  200. * Networking options
  201. */
  202. #define CONFIG_ETHPRIME "eTSEC1"
  203. #define CONFIG_TSEC1 1
  204. #define CONFIG_TSEC1_NAME "eTSEC1"
  205. #define TSEC1_FLAGS TSEC_GIGABIT
  206. #define TSEC1_PHY_ADDR 1
  207. #define TSEC1_PHYIDX 0
  208. #define CONFIG_HAS_ETH0
  209. #define CONFIG_TSEC2 1
  210. #define CONFIG_TSEC2_NAME "eTSEC2"
  211. #define TSEC2_FLAGS TSEC_GIGABIT
  212. #define TSEC2_PHY_ADDR 2
  213. #define TSEC2_PHYIDX 0
  214. #define CONFIG_HAS_ETH1
  215. #define CONFIG_TSEC3 1
  216. #define CONFIG_TSEC3_NAME "eTSEC3"
  217. #define TSEC3_FLAGS TSEC_GIGABIT
  218. #define TSEC3_PHY_ADDR 3
  219. #define TSEC3_PHYIDX 0
  220. #define CONFIG_HAS_ETH2
  221. #define CONFIG_TSEC4 1
  222. #define CONFIG_TSEC4_NAME "eTSEC4"
  223. #define TSEC4_FLAGS TSEC_GIGABIT
  224. #define TSEC4_PHY_ADDR 4
  225. #define TSEC4_PHYIDX 0
  226. #define CONFIG_HAS_ETH3
  227. /*
  228. * BOOTP options
  229. */
  230. #define CONFIG_BOOTP_BOOTFILESIZE
  231. /*
  232. * Miscellaneous configurable options
  233. */
  234. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  235. #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
  236. #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
  237. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  238. /*
  239. * For booting Linux, the board info and command line data
  240. * have to be in the first 16 MB of memory, since this is
  241. * the maximum mapped by the Linux kernel during initialization.
  242. */
  243. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  244. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  245. /*
  246. * Environment Configuration
  247. */
  248. /*
  249. * Flash memory map:
  250. * fff80000 - ffffffff Pri U-Boot (512 KB)
  251. * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
  252. * fff00000 - fff3ffff Pri FDT (256KB)
  253. * fef00000 - ffefffff Pri OS image (16MB)
  254. * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
  255. *
  256. * fbf80000 - fbffffff Sec U-Boot (512 KB)
  257. * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
  258. * fbf00000 - fbf3ffff Sec FDT (256KB)
  259. * faf00000 - fbefffff Sec OS image (16MB)
  260. * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
  261. */
  262. #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
  263. #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
  264. #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
  265. #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
  266. #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
  267. #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
  268. #define CONFIG_PROG_UBOOT1 \
  269. "$download_cmd $loadaddr $ubootfile; " \
  270. "if test $? -eq 0; then " \
  271. "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  272. "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  273. "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
  274. "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
  275. "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
  276. "if test $? -ne 0; then " \
  277. "echo PROGRAM FAILED; " \
  278. "else; " \
  279. "echo PROGRAM SUCCEEDED; " \
  280. "fi; " \
  281. "else; " \
  282. "echo DOWNLOAD FAILED; " \
  283. "fi;"
  284. #define CONFIG_PROG_UBOOT2 \
  285. "$download_cmd $loadaddr $ubootfile; " \
  286. "if test $? -eq 0; then " \
  287. "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  288. "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  289. "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
  290. "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
  291. "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
  292. "if test $? -ne 0; then " \
  293. "echo PROGRAM FAILED; " \
  294. "else; " \
  295. "echo PROGRAM SUCCEEDED; " \
  296. "fi; " \
  297. "else; " \
  298. "echo DOWNLOAD FAILED; " \
  299. "fi;"
  300. #define CONFIG_BOOT_OS_NET \
  301. "$download_cmd $osaddr $osfile; " \
  302. "if test $? -eq 0; then " \
  303. "if test -n $fdtaddr; then " \
  304. "$download_cmd $fdtaddr $fdtfile; " \
  305. "if test $? -eq 0; then " \
  306. "bootm $osaddr - $fdtaddr; " \
  307. "else; " \
  308. "echo FDT DOWNLOAD FAILED; " \
  309. "fi; " \
  310. "else; " \
  311. "bootm $osaddr; " \
  312. "fi; " \
  313. "else; " \
  314. "echo OS DOWNLOAD FAILED; " \
  315. "fi;"
  316. #define CONFIG_PROG_OS1 \
  317. "$download_cmd $osaddr $osfile; " \
  318. "if test $? -eq 0; then " \
  319. "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
  320. "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  321. "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
  322. "if test $? -ne 0; then " \
  323. "echo OS PROGRAM FAILED; " \
  324. "else; " \
  325. "echo OS PROGRAM SUCCEEDED; " \
  326. "fi; " \
  327. "else; " \
  328. "echo OS DOWNLOAD FAILED; " \
  329. "fi;"
  330. #define CONFIG_PROG_OS2 \
  331. "$download_cmd $osaddr $osfile; " \
  332. "if test $? -eq 0; then " \
  333. "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
  334. "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  335. "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
  336. "if test $? -ne 0; then " \
  337. "echo OS PROGRAM FAILED; " \
  338. "else; " \
  339. "echo OS PROGRAM SUCCEEDED; " \
  340. "fi; " \
  341. "else; " \
  342. "echo OS DOWNLOAD FAILED; " \
  343. "fi;"
  344. #define CONFIG_PROG_FDT1 \
  345. "$download_cmd $fdtaddr $fdtfile; " \
  346. "if test $? -eq 0; then " \
  347. "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
  348. "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  349. "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
  350. "if test $? -ne 0; then " \
  351. "echo FDT PROGRAM FAILED; " \
  352. "else; " \
  353. "echo FDT PROGRAM SUCCEEDED; " \
  354. "fi; " \
  355. "else; " \
  356. "echo FDT DOWNLOAD FAILED; " \
  357. "fi;"
  358. #define CONFIG_PROG_FDT2 \
  359. "$download_cmd $fdtaddr $fdtfile; " \
  360. "if test $? -eq 0; then " \
  361. "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
  362. "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  363. "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
  364. "if test $? -ne 0; then " \
  365. "echo FDT PROGRAM FAILED; " \
  366. "else; " \
  367. "echo FDT PROGRAM SUCCEEDED; " \
  368. "fi; " \
  369. "else; " \
  370. "echo FDT DOWNLOAD FAILED; " \
  371. "fi;"
  372. #define CONFIG_EXTRA_ENV_SETTINGS \
  373. "autoload=yes\0" \
  374. "download_cmd=tftp\0" \
  375. "console_args=console=ttyS0,115200\0" \
  376. "root_args=root=/dev/nfs rw\0" \
  377. "misc_args=ip=on\0" \
  378. "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
  379. "bootfile=/home/user/file\0" \
  380. "osfile=/home/user/board.uImage\0" \
  381. "fdtfile=/home/user/board.dtb\0" \
  382. "ubootfile=/home/user/u-boot.bin\0" \
  383. "fdtaddr=0x1e00000\0" \
  384. "osaddr=0x1000000\0" \
  385. "loadaddr=0x1000000\0" \
  386. "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
  387. "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
  388. "prog_os1="CONFIG_PROG_OS1"\0" \
  389. "prog_os2="CONFIG_PROG_OS2"\0" \
  390. "prog_fdt1="CONFIG_PROG_FDT1"\0" \
  391. "prog_fdt2="CONFIG_PROG_FDT2"\0" \
  392. "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
  393. "bootcmd_flash1=run set_bootargs; " \
  394. "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
  395. "bootcmd_flash2=run set_bootargs; " \
  396. "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
  397. "bootcmd=run bootcmd_flash1\0"
  398. #endif /* __CONFIG_H */