xilinx_zynqmp_r5.h 1003 B

12345678910111213141516171819202122232425262728293031323334353637
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * (C) Copyright 2018 Xilinx, Inc. (Michal Simek)
  4. */
  5. #ifndef __CONFIG_ZYNQMP_R5_H
  6. #define __CONFIG_ZYNQMP_R5_H
  7. #define CONFIG_EXTRA_ENV_SETTINGS
  8. /* CPU clock */
  9. #define CONFIG_CPU_FREQ_HZ 500000000
  10. /* Serial drivers */
  11. /* The following table includes the supported baudrates */
  12. #define CONFIG_SYS_BAUDRATE_TABLE \
  13. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
  14. /* Boot configuration */
  15. #define CONFIG_SYS_LOAD_ADDR 0 /* default? */
  16. #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  17. #define CONFIG_SYS_MALLOC_LEN 0x1400000
  18. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  19. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  20. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  21. CONFIG_SYS_INIT_RAM_SIZE - \
  22. GENERATED_GBL_DATA_SIZE)
  23. /* Extend size of kernel image for uncompression */
  24. #define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
  25. #define CONFIG_SKIP_LOWLEVEL_INIT
  26. #endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */