vme8349.h 9.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * esd vme8349 U-Boot configuration file
  4. * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
  5. *
  6. * (C) Copyright 2006-2010
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * reinhard.arlt@esd-electronics.de
  10. * Based on the MPC8349EMDS config.
  11. */
  12. /*
  13. * vme8349 board configuration file.
  14. */
  15. #ifndef __CONFIG_H
  16. #define __CONFIG_H
  17. /*
  18. * High Level Configuration Options
  19. */
  20. #define CONFIG_E300 1 /* E300 Family */
  21. /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  22. #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
  23. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  24. /*
  25. * DDR Setup
  26. */
  27. #define CONFIG_DDR_ECC /* only for ECC DDR module */
  28. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  29. #define CONFIG_SPD_EEPROM
  30. #define SPD_EEPROM_ADDRESS 0x54
  31. #define CONFIG_SYS_READ_SPD vme8349_read_spd
  32. #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
  33. /*
  34. * 32-bit data path mode.
  35. *
  36. * Please note that using this mode for devices with the real density of 64-bit
  37. * effectively reduces the amount of available memory due to the effect of
  38. * wrapping around while translating address to row/columns, for example in the
  39. * 256MB module the upper 128MB get aliased with contents of the lower
  40. * 128MB); normally this define should be used for devices with real 32-bit
  41. * data path.
  42. */
  43. #undef CONFIG_DDR_32BIT
  44. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/
  45. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  46. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  47. #define CONFIG_DDR_2T_TIMING
  48. #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
  49. | DDRCDR_ODT \
  50. | DDRCDR_Q_DRN)
  51. /* 0x80080001 */
  52. /*
  53. * FLASH on the Local Bus
  54. */
  55. #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
  56. #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
  57. #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
  58. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  59. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
  60. #undef CONFIG_SYS_FLASH_CHECKSUM
  61. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
  62. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
  63. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  64. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  65. #define CONFIG_SYS_RAMBOOT
  66. #else
  67. #undef CONFIG_SYS_RAMBOOT
  68. #endif
  69. #define CONFIG_SYS_INIT_RAM_LOCK 1
  70. #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
  71. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
  72. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  73. GENERATED_GBL_DATA_SIZE)
  74. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  75. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
  76. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
  77. #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
  78. /*
  79. * Serial Port
  80. */
  81. #define CONFIG_SYS_NS16550_SERIAL
  82. #define CONFIG_SYS_NS16550_REG_SIZE 1
  83. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  84. #define CONFIG_SYS_BAUDRATE_TABLE \
  85. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  86. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  87. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  88. /* I2C */
  89. #define CONFIG_SYS_I2C
  90. #define CONFIG_SYS_I2C_FSL
  91. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  92. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  93. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  94. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  95. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  96. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  97. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  98. /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
  99. #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
  100. /* TSEC */
  101. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  102. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  103. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  104. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
  105. /*
  106. * General PCI
  107. * Addresses are mapped 1-1.
  108. */
  109. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  110. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  111. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  112. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  113. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  114. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  115. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  116. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  117. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  118. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  119. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  120. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  121. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  122. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  123. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  124. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  125. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  126. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  127. #if defined(CONFIG_PCI)
  128. #if !defined(CONFIG_PCI_PNP)
  129. #define PCI_ENET0_IOADDR 0xFIXME
  130. #define PCI_ENET0_MEMADDR 0xFIXME
  131. #define PCI_IDSEL_NUMBER 0xFIXME
  132. #endif
  133. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  134. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  135. #endif /* CONFIG_PCI */
  136. /*
  137. * TSEC configuration
  138. */
  139. #if defined(CONFIG_TSEC_ENET)
  140. #define CONFIG_GMII /* MII PHY management */
  141. #define CONFIG_TSEC1
  142. #define CONFIG_TSEC1_NAME "TSEC0"
  143. #define CONFIG_TSEC2
  144. #define CONFIG_TSEC2_NAME "TSEC1"
  145. #define CONFIG_PHY_M88E1111
  146. #define TSEC1_PHY_ADDR 0x08
  147. #define TSEC2_PHY_ADDR 0x10
  148. #define TSEC1_PHYIDX 0
  149. #define TSEC2_PHYIDX 0
  150. #define TSEC1_FLAGS TSEC_GIGABIT
  151. #define TSEC2_FLAGS TSEC_GIGABIT
  152. /* Options are: TSEC[0-1] */
  153. #define CONFIG_ETHPRIME "TSEC0"
  154. #endif /* CONFIG_TSEC_ENET */
  155. /*
  156. * Environment
  157. */
  158. #ifndef CONFIG_SYS_RAMBOOT
  159. /* Address and size of Redundant Environment Sector */
  160. #endif
  161. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  162. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  163. /*
  164. * BOOTP options
  165. */
  166. #define CONFIG_BOOTP_BOOTFILESIZE
  167. #define CONFIG_SYS_RTC_BUS_NUM 0x01
  168. #define CONFIG_SYS_I2C_RTC_ADDR 0x32
  169. /* Pass Ethernet MAC to VxWorks */
  170. #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
  171. #undef CONFIG_WATCHDOG /* watchdog disabled */
  172. /*
  173. * Miscellaneous configurable options
  174. */
  175. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  176. /*
  177. * For booting Linux, the board info and command line data
  178. * have to be in the first 256 MB of memory, since this is
  179. * the maximum mapped by the Linux kernel during initialization.
  180. */
  181. #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
  182. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  183. /* System IO Config */
  184. #define CONFIG_SYS_SICRH 0
  185. #define CONFIG_SYS_SICRL SICRL_LDP_A
  186. #define CONFIG_SYS_GPIO1_PRELIM
  187. #define CONFIG_SYS_GPIO1_DIR 0x00100000
  188. #define CONFIG_SYS_GPIO1_DAT 0x00100000
  189. #define CONFIG_SYS_GPIO2_PRELIM
  190. #define CONFIG_SYS_GPIO2_DIR 0x78900000
  191. #define CONFIG_SYS_GPIO2_DAT 0x70100000
  192. #ifdef CONFIG_PCI
  193. #define CONFIG_PCI_INDIRECT_BRIDGE
  194. #endif
  195. #if defined(CONFIG_CMD_KGDB)
  196. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  197. #endif
  198. /*
  199. * Environment Configuration
  200. */
  201. #if defined(CONFIG_TSEC_ENET)
  202. #define CONFIG_HAS_ETH0
  203. #define CONFIG_HAS_ETH1
  204. #endif
  205. #define CONFIG_HOSTNAME "VME8349"
  206. #define CONFIG_ROOTPATH "/tftpboot/rootfs"
  207. #define CONFIG_BOOTFILE "uImage"
  208. #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
  209. #define CONFIG_EXTRA_ENV_SETTINGS \
  210. "netdev=eth0\0" \
  211. "hostname=vme8349\0" \
  212. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  213. "nfsroot=${serverip}:${rootpath}\0" \
  214. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  215. "addip=setenv bootargs ${bootargs} " \
  216. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  217. ":${hostname}:${netdev}:off panic=1\0" \
  218. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  219. "flash_nfs=run nfsargs addip addtty;" \
  220. "bootm ${kernel_addr}\0" \
  221. "flash_self=run ramargs addip addtty;" \
  222. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  223. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  224. "bootm\0" \
  225. "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
  226. "update=protect off fff00000 fff3ffff; " \
  227. "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
  228. "upd=run load update\0" \
  229. "fdtaddr=780000\0" \
  230. "fdtfile=vme8349.dtb\0" \
  231. ""
  232. #define CONFIG_NFSBOOTCOMMAND \
  233. "setenv bootargs root=/dev/nfs rw " \
  234. "nfsroot=$serverip:$rootpath " \
  235. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  236. "$netdev:off " \
  237. "console=$consoledev,$baudrate $othbootargs;" \
  238. "tftp $loadaddr $bootfile;" \
  239. "tftp $fdtaddr $fdtfile;" \
  240. "bootm $loadaddr - $fdtaddr"
  241. #define CONFIG_RAMBOOTCOMMAND \
  242. "setenv bootargs root=/dev/ram rw " \
  243. "console=$consoledev,$baudrate $othbootargs;" \
  244. "tftp $ramdiskaddr $ramdiskfile;" \
  245. "tftp $loadaddr $bootfile;" \
  246. "tftp $fdtaddr $fdtfile;" \
  247. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  248. #define CONFIG_BOOTCOMMAND "run flash_self"
  249. #ifndef __ASSEMBLY__
  250. int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
  251. unsigned char *buffer, int len);
  252. #endif
  253. #endif /* __CONFIG_H */