vexpress_aemv8a.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Configuration for Versatile Express. Parts were derived from other ARM
  4. * configurations.
  5. */
  6. #ifndef __VEXPRESS_AEMV8A_H
  7. #define __VEXPRESS_AEMV8A_H
  8. #define CONFIG_REMAKE_ELF
  9. /* Link Definitions */
  10. #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  11. /* ATF loads u-boot here for BASE_FVP model */
  12. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  13. #elif CONFIG_TARGET_VEXPRESS64_JUNO
  14. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  15. #endif
  16. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  17. /* CS register bases for the original memory map. */
  18. #define V2M_PA_CS0 0x00000000
  19. #define V2M_PA_CS1 0x14000000
  20. #define V2M_PA_CS2 0x18000000
  21. #define V2M_PA_CS3 0x1c000000
  22. #define V2M_PA_CS4 0x0c000000
  23. #define V2M_PA_CS5 0x10000000
  24. #define V2M_PERIPH_OFFSET(x) (x << 16)
  25. #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  26. #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  27. #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  28. #define V2M_BASE 0x80000000
  29. /* Common peripherals relative to CS7. */
  30. #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  31. #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  32. #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  33. #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  34. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  35. #define V2M_UART0 0x7ff80000
  36. #define V2M_UART1 0x7ff70000
  37. #else /* Not Juno */
  38. #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  39. #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  40. #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  41. #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  42. #endif
  43. #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  44. #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  45. #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  46. #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  47. #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  48. #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  49. #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  50. /* System register offsets. */
  51. #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
  52. #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
  53. #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
  54. /* Generic Timer Definitions */
  55. #define COUNTER_FREQUENCY 24000000 /* 24MHz */
  56. /* Generic Interrupt Controller Definitions */
  57. #ifdef CONFIG_GICV3
  58. #define GICD_BASE (0x2f000000)
  59. #define GICR_BASE (0x2f100000)
  60. #else
  61. #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  62. #define GICD_BASE (0x2f000000)
  63. #define GICC_BASE (0x2c000000)
  64. #elif CONFIG_TARGET_VEXPRESS64_JUNO
  65. #define GICD_BASE (0x2C010000)
  66. #define GICC_BASE (0x2C02f000)
  67. #endif
  68. #endif /* !CONFIG_GICV3 */
  69. /* Size of malloc() pool */
  70. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
  71. #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
  72. /* The Vexpress64 simulators use SMSC91C111 */
  73. #define CONFIG_SMC91111 1
  74. #define CONFIG_SMC91111_BASE (0x01A000000)
  75. #endif
  76. /* PL011 Serial Configuration */
  77. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  78. #define CONFIG_PL011_CLOCK 7372800
  79. #else
  80. #define CONFIG_PL011_CLOCK 24000000
  81. #endif
  82. /* BOOTP options */
  83. #define CONFIG_BOOTP_BOOTFILESIZE
  84. /* Miscellaneous configurable options */
  85. #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
  86. /* Physical Memory Map */
  87. #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
  88. /* Top 16MB reserved for secure world use */
  89. #define DRAM_SEC_SIZE 0x01000000
  90. #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
  91. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  92. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  93. #define PHYS_SDRAM_2 (0x880000000)
  94. #define PHYS_SDRAM_2_SIZE 0x180000000
  95. #endif
  96. /* Enable memtest */
  97. /* Initial environment variables */
  98. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  99. /*
  100. * Defines where the kernel and FDT exist in NOR flash and where it will
  101. * be copied into DRAM
  102. */
  103. #define CONFIG_EXTRA_ENV_SETTINGS \
  104. "kernel_name=norkern\0" \
  105. "kernel_alt_name=Image\0" \
  106. "kernel_addr_r=0x80080000\0" \
  107. "ramdisk_name=ramdisk.img\0" \
  108. "ramdisk_addr_r=0x88000000\0" \
  109. "fdtfile=board.dtb\0" \
  110. "fdt_alt_name=juno\0" \
  111. "fdt_addr_r=0x80000000\0" \
  112. /* Copy the kernel and FDT to DRAM memory and boot */
  113. #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\
  114. "if test $? -eq 1; then "\
  115. " echo Loading ${kernel_alt_name} instead of "\
  116. "${kernel_name}; "\
  117. " afs load ${kernel_alt_name} ${kernel_addr_r};"\
  118. "fi ; "\
  119. "afs load ${fdtfile} ${fdt_addr_r} ;"\
  120. "if test $? -eq 1; then "\
  121. " echo Loading ${fdt_alt_name} instead of "\
  122. "${fdtfile}; "\
  123. " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
  124. "fi ; "\
  125. "fdt addr ${fdt_addr_r}; fdt resize; " \
  126. "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
  127. "then "\
  128. " setenv ramdisk_param ${ramdisk_addr_r}; "\
  129. " else setenv ramdisk_param -; "\
  130. "fi ; " \
  131. "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}"
  132. #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
  133. #define CONFIG_EXTRA_ENV_SETTINGS \
  134. "kernel_name=Image\0" \
  135. "kernel_addr=0x80080000\0" \
  136. "initrd_name=ramdisk.img\0" \
  137. "initrd_addr=0x88000000\0" \
  138. "fdtfile=devtree.dtb\0" \
  139. "fdt_addr=0x83000000\0" \
  140. "boot_name=boot.img\0" \
  141. "boot_addr=0x8007f800\0"
  142. #define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
  143. " set bootargs; " \
  144. " abootimg addr ${boot_addr}; " \
  145. " abootimg get dtb --index=0 fdt_addr; " \
  146. " bootm ${boot_addr} ${boot_addr} " \
  147. " ${fdt_addr}; " \
  148. "else; " \
  149. " set fdt_high 0xffffffffffffffff; " \
  150. " set initrd_high 0xffffffffffffffff; " \
  151. " smhload ${kernel_name} ${kernel_addr}; " \
  152. " smhload ${fdtfile} ${fdt_addr}; " \
  153. " smhload ${initrd_name} ${initrd_addr} "\
  154. " initrd_end; " \
  155. " fdt addr ${fdt_addr}; fdt resize; " \
  156. " fdt chosen ${initrd_addr} ${initrd_end}; " \
  157. " booti $kernel_addr - $fdt_addr; " \
  158. "fi"
  159. #endif
  160. /* Monitor Command Prompt */
  161. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  162. #define CONFIG_SYS_MAXARGS 64 /* max command args */
  163. #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  164. #define CONFIG_SYS_FLASH_BASE 0x08000000
  165. /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
  166. #define CONFIG_SYS_MAX_FLASH_SECT 259
  167. /* Store environment at top of flash in the same location as blank.img */
  168. /* in the Juno firmware. */
  169. #else
  170. #define CONFIG_SYS_FLASH_BASE 0x0C000000
  171. /* 256 x 256KiB sectors */
  172. #define CONFIG_SYS_MAX_FLASH_SECT 256
  173. /* Store environment at top of flash */
  174. #endif
  175. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
  176. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  177. #ifdef CONFIG_USB_EHCI_HCD
  178. #define CONFIG_USB_OHCI_NEW
  179. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
  180. #endif
  181. #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
  182. #define FLASH_MAX_SECTOR_SIZE 0x00040000
  183. #endif /* __VEXPRESS_AEMV8A_H */