ve8313.h 7.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. *
  5. * (C) Copyright 2010
  6. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  7. */
  8. /*
  9. * ve8313 board configuration file
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. #include <linux/stringify.h>
  14. /*
  15. * High Level Configuration Options
  16. */
  17. #define CONFIG_E300 1
  18. #define CONFIG_PCI_INDIRECT_BRIDGE 1
  19. /*
  20. * On-board devices
  21. *
  22. */
  23. /*
  24. * Device configurations
  25. */
  26. /*
  27. * DDR Setup
  28. */
  29. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  30. /*
  31. * Manually set up DDR parameters, as this board does not
  32. * have the SPD connected to I2C.
  33. */
  34. #define CONFIG_SYS_DDR_SIZE 128 /* MB */
  35. #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
  36. | CSCONFIG_AP \
  37. | CSCONFIG_ODT_RD_NEVER \
  38. | CSCONFIG_ODT_WR_ALL \
  39. | CSCONFIG_ROW_BIT_13 \
  40. | CSCONFIG_COL_BIT_10)
  41. /* 0x80840102 */
  42. #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  43. #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  44. | (0 << TIMING_CFG0_WRT_SHIFT) \
  45. | (3 << TIMING_CFG0_RRT_SHIFT) \
  46. | (2 << TIMING_CFG0_WWT_SHIFT) \
  47. | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  48. | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  49. | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  50. | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  51. /* 0x0e720802 */
  52. #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  53. | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  54. | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  55. | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  56. | (6 << TIMING_CFG1_REFREC_SHIFT) \
  57. | (2 << TIMING_CFG1_WRREC_SHIFT) \
  58. | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  59. | (2 << TIMING_CFG1_WRTORD_SHIFT))
  60. /* 0x26256222 */
  61. #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  62. | (5 << TIMING_CFG2_CPO_SHIFT) \
  63. | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  64. | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  65. | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  66. | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  67. | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  68. /* 0x029028c7 */
  69. #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
  70. | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  71. /* 0x03202000 */
  72. #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \
  73. | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  74. | SDRAM_CFG_DBW_32)
  75. /* 0x43080000 */
  76. #define CONFIG_SYS_SDRAM_CFG2 0x00401000
  77. #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
  78. | (0x0232 << SDRAM_MODE_SD_SHIFT))
  79. /* 0x44400232 */
  80. #define CONFIG_SYS_DDR_MODE_2 0x8000C000
  81. #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  82. /*0x02000000*/
  83. #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  84. | DDRCDR_PZ_NOMZ \
  85. | DDRCDR_NZ_NOMZ \
  86. | DDRCDR_M_ODR)
  87. /* 0x73000002 */
  88. /*
  89. * FLASH on the Local Bus
  90. */
  91. #define CONFIG_SYS_FLASH_BASE 0xFE000000
  92. #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */
  93. #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
  94. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  95. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */
  96. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  97. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  98. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  99. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  100. #define CONFIG_SYS_RAMBOOT
  101. #endif
  102. #define CONFIG_SYS_INIT_RAM_LOCK 1
  103. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
  104. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  105. #define CONFIG_SYS_GBL_DATA_OFFSET \
  106. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  107. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  108. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  109. #define CONFIG_SYS_MONITOR_LEN (384 * 1024)
  110. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  111. /*
  112. * NAND settings
  113. */
  114. #define CONFIG_SYS_NAND_BASE 0x61000000
  115. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  116. #define CONFIG_NAND_FSL_ELBC 1
  117. #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
  118. /* Still needed for spl_minimal.c */
  119. #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
  120. #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
  121. /*
  122. * Serial Port
  123. */
  124. #define CONFIG_SYS_NS16550_SERIAL
  125. #define CONFIG_SYS_NS16550_REG_SIZE 1
  126. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  127. #define CONFIG_SYS_BAUDRATE_TABLE \
  128. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  129. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  130. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  131. #if defined(CONFIG_PCI)
  132. /*
  133. * General PCI
  134. * Addresses are mapped 1-1.
  135. */
  136. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  137. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  138. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  139. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  140. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  141. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  142. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  143. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  144. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  145. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  146. #endif
  147. /*
  148. * TSEC
  149. */
  150. #define CONFIG_TSEC1
  151. #ifdef CONFIG_TSEC1
  152. #define CONFIG_HAS_ETH0
  153. #define CONFIG_TSEC1_NAME "TSEC1"
  154. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  155. #define TSEC1_PHY_ADDR 0x01
  156. #define TSEC1_FLAGS 0
  157. #define TSEC1_PHYIDX 0
  158. #endif
  159. /* Options are: TSEC[0-1] */
  160. #define CONFIG_ETHPRIME "TSEC1"
  161. /*
  162. * Environment
  163. */
  164. /* Address and size of Redundant Environment Sector */
  165. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  166. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  167. /*
  168. * BOOTP options
  169. */
  170. #define CONFIG_BOOTP_BOOTFILESIZE
  171. /*
  172. * Miscellaneous configurable options
  173. */
  174. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  175. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  176. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
  177. /*
  178. * For booting Linux, the board info and command line data
  179. * have to be in the first 256 MB of memory, since this is
  180. * the maximum mapped by the Linux kernel during initialization.
  181. */
  182. /* Initial Memory map for Linux*/
  183. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  184. /* System IO Config */
  185. #define CONFIG_SYS_SICRH (0x01000000 | \
  186. SICRH_ETSEC2_B | \
  187. SICRH_ETSEC2_C | \
  188. SICRH_ETSEC2_D | \
  189. SICRH_ETSEC2_E | \
  190. SICRH_ETSEC2_F | \
  191. SICRH_ETSEC2_G | \
  192. SICRH_TSOBI1 | \
  193. SICRH_TSOBI2)
  194. /* 0x010fff03 */
  195. #define CONFIG_SYS_SICRL (SICRL_LBC | \
  196. SICRL_SPI_A | \
  197. SICRL_SPI_B | \
  198. SICRL_SPI_C | \
  199. SICRL_SPI_D | \
  200. SICRL_ETSEC2_A)
  201. /* 0x33fc0003) */
  202. #define CONFIG_NETDEV eth0
  203. #define CONFIG_HOSTNAME "ve8313"
  204. #define CONFIG_UBOOTPATH ve8313/u-boot.bin
  205. #define CONFIG_EXTRA_ENV_SETTINGS \
  206. "netdev=" __stringify(CONFIG_NETDEV) "\0" \
  207. "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
  208. "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  209. "u-boot_addr_r=100000\0" \
  210. "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
  211. "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
  212. " +${filesize};" \
  213. "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
  214. "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
  215. " ${filesize};" \
  216. "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
  217. #endif /* __CONFIG_H */