ti816x_evm.h 2.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * ti816x_evm.h
  4. *
  5. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  6. * Antoine Tenart, <atenart@adeneo-embedded.com>
  7. */
  8. #ifndef __CONFIG_TI816X_EVM_H
  9. #define __CONFIG_TI816X_EVM_H
  10. #include <configs/ti_armv7_omap.h>
  11. #include <asm/arch/omap.h>
  12. #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
  13. #define CONFIG_EXTRA_ENV_SETTINGS \
  14. DEFAULT_LINUX_BOOT_ENV \
  15. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  16. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  17. #define CONFIG_BOOTCOMMAND \
  18. "mmc rescan;" \
  19. "fatload mmc 0 ${loadaddr} uImage;" \
  20. "bootm ${loadaddr}" \
  21. /* Clock Defines */
  22. #define V_OSCK 24000000 /* Clock output from T2 */
  23. #define V_SCLK (V_OSCK >> 1)
  24. #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
  25. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  26. /**
  27. * Platform/Board specific defs
  28. */
  29. #define CONFIG_SYS_CLK_FREQ 27000000
  30. #define CONFIG_SYS_TIMERBASE 0x4802E000
  31. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  32. /*
  33. * NS16550 Configuration
  34. */
  35. #define CONFIG_SYS_NS16550_SERIAL
  36. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  37. #define CONFIG_SYS_NS16550_CLK (48000000)
  38. #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
  39. /* allow overwriting serial config and ethaddr */
  40. /*
  41. * GPMC NAND block. We support 1 device and the physical address to
  42. * access CS0 at is 0x8000000.
  43. */
  44. #define CONFIG_SYS_NAND_BASE 0x8000000
  45. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  46. /* NAND: SPL related configs */
  47. /* NAND: device related configs */
  48. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  49. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  50. CONFIG_SYS_NAND_PAGE_SIZE)
  51. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  52. #define CONFIG_SYS_NAND_OOBSIZE 64
  53. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  54. /* NAND: driver related configs */
  55. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  56. #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  57. 10, 11, 12, 13, 14, 15, 16, 17, \
  58. 18, 19, 20, 21, 22, 23, 24, 25, \
  59. 26, 27, 28, 29, 30, 31, 32, 33, \
  60. 34, 35, 36, 37, 38, 39, 40, 41, \
  61. 42, 43, 44, 45, 46, 47, 48, 49, \
  62. 50, 51, 52, 53, 54, 55, 56, 57, }
  63. #define CONFIG_SYS_NAND_ECCSIZE 512
  64. #define CONFIG_SYS_NAND_ECCBYTES 14
  65. #define CONFIG_SYS_NAND_ONFI_DETECTION
  66. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
  67. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
  68. #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  69. /* SPL */
  70. /* Defines for SPL */
  71. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  72. CONFIG_SPL_TEXT_BASE)
  73. #define CONFIG_NET_RETRY_COUNT 10
  74. /* Since SPL did pll and ddr initialization for us,
  75. * we don't need to do it twice.
  76. */
  77. #ifndef CONFIG_SPL_BUILD
  78. #define CONFIG_SKIP_LOWLEVEL_INIT
  79. #endif
  80. /*
  81. * Disable MMC DM for SPL build and can be re-enabled after adding
  82. * DM support in SPL
  83. */
  84. #ifdef CONFIG_SPL_BUILD
  85. #undef CONFIG_DM_MMC
  86. #undef CONFIG_TIMER
  87. #endif
  88. #endif