theadorable.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
  4. */
  5. #ifndef _CONFIG_THEADORABLE_H
  6. #define _CONFIG_THEADORABLE_H
  7. /*
  8. * High Level Configuration Options (easy to change)
  9. */
  10. /*
  11. * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  12. * for DDR ECC byte filling in the SPL before loading the main
  13. * U-Boot into it.
  14. */
  15. #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
  16. /*
  17. * The debugging version enables USB support via defconfig.
  18. * This version should also enable all other non-production
  19. * interfaces / features.
  20. */
  21. /* I2C */
  22. #define CONFIG_SYS_I2C
  23. #define CONFIG_SYS_I2C_MVTWSI
  24. #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
  25. #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
  26. #define CONFIG_SYS_I2C_SLAVE 0x0
  27. #define CONFIG_SYS_I2C_SPEED 100000
  28. /* USB/EHCI configuration */
  29. #define CONFIG_EHCI_IS_TDI
  30. #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  31. /* Environment in SPI NOR flash */
  32. #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
  33. /* Keep device tree and initrd in lower memory so the kernel can access them */
  34. #define CONFIG_EXTRA_ENV_SETTINGS \
  35. "fdt_high=0x10000000\0" \
  36. "initrd_high=0x10000000\0"
  37. /* SATA support */
  38. #define CONFIG_SYS_SATA_MAX_DEVICE 1
  39. #define CONFIG_LBA48
  40. /* Enable LCD and reserve 512KB from top of memory*/
  41. #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
  42. /* FPGA programming support */
  43. #define CONFIG_FPGA_STRATIX_V
  44. /*
  45. * Bootcounter
  46. */
  47. /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
  48. #define BOOTCOUNT_ADDR 0x1000
  49. /*
  50. * mv-common.h should be defined after CMD configs since it used them
  51. * to enable certain macros
  52. */
  53. #include "mv-common.h"
  54. /*
  55. * Memory layout while starting into the bin_hdr via the
  56. * BootROM:
  57. *
  58. * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
  59. * 0x4000.4030 bin_hdr start address
  60. * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
  61. * 0x4007.fffc BootROM stack top
  62. *
  63. * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  64. * L2 cache thus cannot be used.
  65. */
  66. /* SPL */
  67. /* Defines for SPL */
  68. #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
  69. #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
  70. #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
  71. #ifdef CONFIG_SPL_BUILD
  72. #define CONFIG_SYS_MALLOC_SIMPLE
  73. #endif
  74. #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
  75. #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
  76. /* SPL related SPI defines */
  77. #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
  78. /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
  79. #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
  80. #endif /* _CONFIG_THEADORABLE_H */