tegra20-common.h 2.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010-2012
  4. * NVIDIA Corporation <www.nvidia.com>
  5. */
  6. #ifndef _TEGRA20_COMMON_H_
  7. #define _TEGRA20_COMMON_H_
  8. #include "tegra-common.h"
  9. /*
  10. * NS16550 Configuration
  11. */
  12. #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
  13. /*
  14. * Miscellaneous configurable options
  15. */
  16. #define CONFIG_STACKBASE 0x03800000 /* 56MB */
  17. /*-----------------------------------------------------------------------
  18. * Physical Memory Map
  19. */
  20. /*
  21. * Memory layout for where various images get loaded by boot scripts:
  22. *
  23. * scriptaddr can be pretty much anywhere that doesn't conflict with something
  24. * else. Put it above BOOTMAPSZ to eliminate conflicts.
  25. *
  26. * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  27. * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  28. *
  29. * kernel_addr_r must be within the first 128M of RAM in order for the
  30. * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  31. * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  32. * should not overlap that area, or the kernel will have to copy itself
  33. * somewhere else before decompression. Similarly, the address of any other
  34. * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  35. * this up to 32M allows for a sizable kernel to be decompressed below the
  36. * compressed load address.
  37. *
  38. * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
  39. * the compressed kernel to be up to 32M too.
  40. *
  41. * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  42. * for the FDT/DTB to be up to 1M, which is hopefully plenty.
  43. */
  44. #define CONFIG_LOADADDR 0x01000000
  45. #define MEM_LAYOUT_ENV_SETTINGS \
  46. "scriptaddr=0x10000000\0" \
  47. "pxefile_addr_r=0x10100000\0" \
  48. "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  49. "fdtfile=" FDTFILE "\0" \
  50. "fdt_addr_r=0x03000000\0" \
  51. "ramdisk_addr_r=0x03100000\0"
  52. /* Defines for SPL */
  53. #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
  54. #define CONFIG_SPL_STACK 0x000ffffc
  55. /* Align LCD to 1MB boundary */
  56. #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
  57. #ifdef CONFIG_TEGRA_LP0
  58. #define TEGRA_LP0_ADDR 0x1C406000
  59. #define TEGRA_LP0_SIZE 0x2000
  60. #define TEGRA_LP0_VEC \
  61. "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
  62. "@" __stringify(TEGRA_LP0_ADDR) " "
  63. #else
  64. #define TEGRA_LP0_VEC
  65. #endif
  66. /*
  67. * This parameter affects a TXFILLTUNING field that controls how much data is
  68. * sent to the latency fifo before it is sent to the wire. Without this
  69. * parameter, the default (2) causes occasional Data Buffer Errors in OUT
  70. * packets depending on the buffer address and size.
  71. */
  72. #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
  73. #define CONFIG_EHCI_IS_TDI
  74. #define CONFIG_SYS_NAND_SELF_INIT
  75. #define CONFIG_SYS_NAND_ONFI_DETECTION
  76. #endif /* _TEGRA20_COMMON_H_ */