socrates.h 9.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2008
  4. * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
  5. *
  6. * Wolfgang Denk <wd@denx.de>
  7. * Copyright 2004 Freescale Semiconductor.
  8. * (C) Copyright 2002,2003 Motorola,Inc.
  9. * Xianghua Xiao <X.Xiao@motorola.com>
  10. */
  11. /*
  12. * Socrates
  13. */
  14. #ifndef __CONFIG_H
  15. #define __CONFIG_H
  16. /* High Level Configuration Options */
  17. #define CONFIG_SOCRATES 1
  18. /*
  19. * Only possible on E500 Version 2 or newer cores.
  20. */
  21. #define CONFIG_ENABLE_36BIT_PHYS 1
  22. /*
  23. * sysclk for MPC85xx
  24. *
  25. * Two valid values are:
  26. * 33000000
  27. * 66000000
  28. *
  29. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  30. * is likely the desired value here, so that is now the default.
  31. * The board, however, can run at 66MHz. In any event, this value
  32. * must match the settings of some switches. Details can be found
  33. * in the README.mpc85xxads.
  34. */
  35. #ifndef CONFIG_SYS_CLK_FREQ
  36. #define CONFIG_SYS_CLK_FREQ 66666666
  37. #endif
  38. /*
  39. * These can be toggled for performance analysis, otherwise use default.
  40. */
  41. #define CONFIG_L2_CACHE /* toggle L2 cache */
  42. #define CONFIG_BTB /* toggle branch predition */
  43. #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  44. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  45. #define CONFIG_SYS_CCSRBAR 0xE0000000
  46. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  47. /* DDR Setup */
  48. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  49. #define CONFIG_DDR_SPD
  50. #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  51. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  52. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  53. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  54. #define CONFIG_VERY_BIG_RAM
  55. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  56. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  57. /* I2C addresses of SPD EEPROMs */
  58. #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
  59. #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
  60. /* Hardcoded values, to use instead of SPD */
  61. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
  62. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
  63. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  64. #define CONFIG_SYS_DDR_TIMING_1 0x3935D322
  65. #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
  66. #define CONFIG_SYS_DDR_MODE 0x00480432
  67. #define CONFIG_SYS_DDR_INTERVAL 0x030C0100
  68. #define CONFIG_SYS_DDR_CONFIG_2 0x04400000
  69. #define CONFIG_SYS_DDR_CONFIG 0xC3008000
  70. #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
  71. #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
  72. /*
  73. * Flash on the LocalBus
  74. */
  75. #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
  76. #define CONFIG_SYS_FLASH_QUIET_TEST
  77. #define CONFIG_SYS_FLASH0 0xFE000000
  78. #define CONFIG_SYS_FLASH1 0xFC000000
  79. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
  80. #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
  81. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
  82. #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
  83. #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
  84. #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
  85. #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
  86. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  87. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
  88. #undef CONFIG_SYS_FLASH_CHECKSUM
  89. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  90. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  91. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  92. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  93. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  94. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  95. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
  96. #define CONFIG_SYS_INIT_RAM_LOCK 1
  97. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  98. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
  99. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  100. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  101. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
  102. #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
  103. /* FPGA and NAND */
  104. #define CONFIG_SYS_FPGA_BASE 0xc0000000
  105. #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
  106. #define CONFIG_SYS_HMI_BASE 0xc0010000
  107. #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
  108. #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
  109. #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
  110. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  111. /* LIME GDC */
  112. #define CONFIG_SYS_LIME_BASE 0xc8000000
  113. #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
  114. #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
  115. #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
  116. #define CONFIG_SYS_SPD_BUS_NUM 0
  117. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  118. /*
  119. * General PCI
  120. * Memory space is mapped 1-1.
  121. */
  122. /* PCI is clocked by the external source at 33 MHz */
  123. #define CONFIG_PCI_CLK_FREQ 33000000
  124. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  125. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  126. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  127. #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
  128. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  129. #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
  130. #define CONFIG_TSEC1 1
  131. #define CONFIG_TSEC1_NAME "TSEC0"
  132. #define CONFIG_TSEC3 1
  133. #define CONFIG_TSEC3_NAME "TSEC1"
  134. #undef CONFIG_MPC85XX_FEC
  135. #define TSEC1_PHY_ADDR 0
  136. #define TSEC3_PHY_ADDR 1
  137. #define TSEC1_PHYIDX 0
  138. #define TSEC3_PHYIDX 0
  139. #define TSEC1_FLAGS TSEC_GIGABIT
  140. #define TSEC3_FLAGS TSEC_GIGABIT
  141. /* Options are: TSEC[0,1] */
  142. #define CONFIG_ETHPRIME "TSEC0"
  143. #define CONFIG_HAS_ETH0
  144. #define CONFIG_HAS_ETH1
  145. /*
  146. * Environment
  147. */
  148. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  149. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  150. #define CONFIG_TIMESTAMP /* Print image info with ts */
  151. /*
  152. * BOOTP options
  153. */
  154. #define CONFIG_BOOTP_BOOTFILESIZE
  155. #undef CONFIG_WATCHDOG /* watchdog disabled */
  156. /*
  157. * Miscellaneous configurable options
  158. */
  159. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  160. /*
  161. * For booting Linux, the board info and command line data
  162. * have to be in the first 8 MB of memory, since this is
  163. * the maximum mapped by the Linux kernel during initialization.
  164. */
  165. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  166. #if defined(CONFIG_CMD_KGDB)
  167. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
  168. #endif
  169. #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
  170. #define CONFIG_EXTRA_ENV_SETTINGS \
  171. "netdev=eth0\0" \
  172. "consdev=ttyS0\0" \
  173. "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
  174. "bootfile=/home/tftp/syscon3/uImage\0" \
  175. "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
  176. "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
  177. "uboot_addr=FFF60000\0" \
  178. "kernel_addr=FE000000\0" \
  179. "fdt_addr=FE1E0000\0" \
  180. "ramdisk_addr=FE200000\0" \
  181. "fdt_addr_r=B00000\0" \
  182. "kernel_addr_r=200000\0" \
  183. "ramdisk_addr_r=400000\0" \
  184. "rootpath=/opt/eldk/ppc_85xxDP\0" \
  185. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  186. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  187. "nfsroot=$serverip:$rootpath\0" \
  188. "addcons=setenv bootargs $bootargs " \
  189. "console=$consdev,$baudrate\0" \
  190. "addip=setenv bootargs $bootargs " \
  191. "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
  192. ":$hostname:$netdev:off panic=1\0" \
  193. "boot_nor=run ramargs addcons;" \
  194. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  195. "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  196. "tftp ${fdt_addr_r} ${fdt_file}; " \
  197. "run nfsargs addip addcons;" \
  198. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  199. "update_uboot=tftp 100000 ${uboot_file};" \
  200. "protect off fff60000 ffffffff;" \
  201. "era fff60000 ffffffff;" \
  202. "cp.b 100000 fff60000 ${filesize};" \
  203. "setenv filesize;saveenv\0" \
  204. "update_kernel=tftp 100000 ${bootfile};" \
  205. "era fe000000 fe1dffff;" \
  206. "cp.b 100000 fe000000 ${filesize};" \
  207. "setenv filesize;saveenv\0" \
  208. "update_fdt=tftp 100000 ${fdt_file};" \
  209. "era fe1e0000 fe1fffff;" \
  210. "cp.b 100000 fe1e0000 ${filesize};" \
  211. "setenv filesize;saveenv\0" \
  212. "update_initrd=tftp 100000 ${initrd_file};" \
  213. "era fe200000 fe9fffff;" \
  214. "cp.b 100000 fe200000 ${filesize};" \
  215. "setenv filesize;saveenv\0" \
  216. "clean_data=era fea00000 fff5ffff\0" \
  217. "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
  218. "load_usb=usb start;" \
  219. "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
  220. "boot_usb=run load_usb usbargs addcons;" \
  221. "bootm ${kernel_addr_r} - ${fdt_addr};" \
  222. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  223. ""
  224. #define CONFIG_BOOTCOMMAND "run boot_nor"
  225. /* pass open firmware flat tree */
  226. /* USB support */
  227. #define CONFIG_USB_OHCI_NEW 1
  228. #define CONFIG_PCI_OHCI 1
  229. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  230. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
  231. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
  232. #endif /* __CONFIG_H */